| 低抖动时钟锁相环的一种优化设计方法 |
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| 引用本文： | 尹海丰,毛志刚.低抖动时钟锁相环的一种优化设计方法[J].固体电子学研究与进展,2010,30(3). |
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| 作者姓名： | 尹海丰 毛志刚 |
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| 作者单位： | 哈尔滨工业大学微电子中心,哈尔滨,150001 |
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| 摘 要： | 重点分析了环路延迟对锁相环稳定性和输出信号抖动性能的影响,提出了一个简单的优化设计方法。用90nmCMOS工艺设计实现了一个基于自偏置技术的时钟锁相环,锁相环可以在很宽的输入频率范围内输出低抖动的时钟信号。
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| 关 键 词： | 锁相环 压控振荡器 自偏置 |
A Design Optimization Method for Low Jitter Clock PLLs |
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| YIN Haifeng,MAO Zhigang.A Design Optimization Method for Low Jitter Clock PLLs[J].Research & Progress of Solid State Electronics,2010,30(3). |
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| Authors: | YIN Haifeng MAO Zhigang |
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| Abstract: | The loop delay's influence to the PLL (Phase-Locked Loop) stability and output signal's jitter performance emphatically is analyzed in this paper. A simple design optimization method is presented. A PLL based on self-biased technology is designed and fabricated in 90 nm CMOS process. The PLL could output low jitter clock signal in a wide input frequency range. |
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| Keywords: | PLL VCO self-biased |
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