| 应用于FPGA的边界扫描设计 |
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| 引用本文： | 蒋晓.应用于FPGA的边界扫描设计[J].中国集成电路,2006,15(8):46-48,17. |
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| 作者姓名： | 蒋晓 |
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| 作者单位： | 中国电子科技集团38研究所 |
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| 摘 要： | 针对在FPGA芯片中的应用特点,设计了一种边界扫描电路,应用于自行设计的FPGA新结构之中。该电路侧重于电路板级测试功能的实现,兼顾芯片功能的测试;同时,加入了器件编程功能。
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| 关 键 词： | 边界扫描 现场可编程门阵列 可测试性设计 器件编程 |
A Boundary-Scan Test Design for FPGA's |
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| Jiang Xiao.A Boundary-Scan Test Design for FPGA''''s[J].China Integrated Circuit,2006,15(8):46-48,17. |
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| Authors: | Jiang Xiao |
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| Affiliation: | Jiang Xiao CETC ECRIEE |
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| Abstract: | A scan_boundary circuit is designed based on the characteristics of FPGA's.The circuit is used in a self_designed new architecture of FPGA.The design emphasizes the function of PCB-level test while paying attention to the chip-level test.And device-programming function is also added into the circuit1 In the design |
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| Keywords: | Boundaryscan FPGA Designfortestability Deviceprogramming |
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