Electrical qualification of new ultrathin integration techniques |
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| Authors: | A Cazarr F Lpinois A Marty S Pinel J Tasselli J P Bailb J R Morante F Murray |
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| Affiliation: | a LAAS-CNRS, 7, Avenue du Colonel Roche, 31077, Toulouse Cedex 4, France;b Dept. d’Electronica, University of Barcelona, Marti i Franquès 1, 08028, Barcelona, Spain;c Philips Semiconductors, 2 rue de la Girafe, BP5120, 14079, Caen Cedex 5, France |
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| Abstract: | The aim of this paper is to analyze the feasibility of ultrathin packages through the electrical qualification of the technological process used, i.e. mechanical lapping. It considers polysilicon bipolar transistors which thickness can reach values lower than 10 μm. Forward mode and reverse mode characterizations show no significant degradation of pertinent characteristics, thus allowing to find applications in new compact packaging concept. |
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