New substrate-triggered ESD protection structures in a 0.18-μm CMOS process without extra mask

In order to quickly discharge the electrostatic discharge (ESD) energy, new substrate-triggered ESD protection structures are proposed in this work. Under transmission line pulsing (TLP) stress, the trigger voltage, turn-on speed and second breakdown current can be obviously improved, as compared with the traditional protection structures. From the experimental results, the new designs have proven a more effective ESD robustness. Moreover there is no need to add any extra mask or do any process modification for the new structures. The proposed new substrate-triggered structures have been verified in foundry’s 0.18-μm CMOS process.