| 12位100MS/s ADC中采样/保持电路的分析与设计 |
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| 引用本文： | 张凯,周贵贤,刘烨,陈贵灿,程军.12位100MS/s ADC中采样/保持电路的分析与设计[J].微电子学与计算机,2007,24(11):8-13. |
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| 作者姓名： | 张凯 周贵贤 刘烨 陈贵灿 程军 |
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| 作者单位： | 西安交通大学,微电子研究所,陕西,西安,710049 |
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| 基金项目： | 西安市应用材料创新基金 |
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| 摘 要： | 设计了一种高性能的采样保持(S/H)电路,在1.8V的电源电压下,其性能满足12位精度、100MS/s转换速率的ADC的要求。设计中采用了一种新型的自举采样开关,提高了S/H电路的可靠性和线性度;对于高增益大带宽的运算跨导放大器OTA的带宽设计,在分析了主运放和辅助运放在带宽和相位裕度等方面的关系的基础上,提出了新的设计方法。仿真结果表明:S/H电路的差动输出摆幅达到了2V;对于输入为49MHz的正弦波,测得其信号噪声失真比达到了82dB,满足12位ADC的要求;整个电路的功耗约为20mW。
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| 关 键 词： | 采样/保持电路 自举开关 增益提高技术 |
| 文章编号： | 1000-7180（2007）11-0008-06 |
| 修稿时间： | 2006-11-24 |
A Sample-and-Hole Circuit for Analysis and Design of a 12bit 100Ms/s ADC |
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| ZHANG Kai,ZHOU Gui-xian,LIU Ye,CHEN Gui-can,CHENG Jun.A Sample-and-Hole Circuit for Analysis and Design of a 12bit 100Ms/s ADC[J].Microelectronics & Computer,2007,24(11):8-13. |
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| Authors: | ZHANG Kai ZHOU Gui-xian LIU Ye CHEN Gui-can CHENG Jun |
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| Abstract: | This paper presents a sample-and-hole(S/H) circuit for a 12-bit, 100MS/s ADC under 1.8V supply voltage. A novel bootstrapped switch is used to improve the reliability and linearity in the S/H circuit. For the design of the operational transconductance amplifier(OTA) with high-gain and wideband, we implement a new design method based on optimizing the bandwidths and phase margins of the main amplifier and the auxiliary amplifier. Simulation results show that the peak signal-to-noise-and-distortion(SNDR) is 82dB with a 49MHz sinusoidal input, the differential output swing of the OTA achieves as high as 2V, and power dissipation of the whole circuit is 20mW. |
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| Keywords: | sample-and-hold circuit bootstrapped switch gain-boosting |
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