Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores |
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Authors: | Yung-Chia Lin Chia Han Lu Chung-Ju Wu Chung-Lin Tang Yi-Ping You Ya-Chaio Moo Jenq-Kuen Lee |
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Affiliation: | (1) Department of Computer Science, National Tsing-Hua University, Hsinchu, 30013, Taiwan |
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Abstract: | The compiler is generally regarded as the most important software component that supports a processor design to achieve success.
This paper describes our application of the open research compiler infrastructure to a novel VLIW DSP (known as the PAC DSP
core) and the specific design of code generation for its register file architecture. The PAC DSP utilizes port-restricted,
distributed, and partitioned register file structures in addition to a heterogeneous clustered data-path architecture to attain
low power consumption and a smaller die. As part of an effort to overcome the new challenges of code generation for the PAC
DSP, we have developed a new register allocation scheme and other retargeting optimization phases that allow the effective
generation of high quality code. Our preliminary experimental results indicate that our developed compiler can efficiently
utilize the features of the specific register file architectures in the PAC DSP. Our experiences in designing compiler support
for the PAC VLIW DSP with irregular resource constraints may also be of interest to those involved in developing compilers
for similar architectures.
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Keywords: | compiler ping-pong register files VLIW DSP clustering parallel processing |
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