CPT原子钟系统的数字正交解调算法及实现

介绍了将数字正交解调算法应用于CPT原子钟系统的锁相环路,通过FPGA硬件结构实现解调功能所开展的研究.经MATLAB和QUARTUS2的联合仿真表明,该算法抗噪声能力强,解调结果可靠性高,是应用于高性能CPT原子钟的理想算法.实际应用于CPT原子钟的实验结果与理论预期和实验仿真结果相一致.该方案有利于原子频标的工作状态调整和保持产品性能一致性.

The Algorithm and Realization of Digital Quadrature Demodulation in CPT Atomic Clock

The study of applying digital quadrature demodulation algorithm to phase locked loop of CPT atomic clock realized with a FPGA core is presented Simulation results for this scheme with both MATLAB and QUARTUS2 reveal its good noise resisting property and reliable demodulation ability Therefore, it is an ideal scheme for high performance CPT atomic clock Experimental result of application the scheme to CPT atomic clock consists with that from simulation This scheme makes it easier to modify the operation state of atomic clock and keeps better consistency of products.