Modeling of Thermally Induced Stresses in Three-Dimensional Bonded Integrated Circuit Wafers

A finite-element model has been developed to investigate the potential reliability issues of thermally induced stresses in interwafer Cu via structures in three-dimensional (3D) integrated circuit (IC) wafers. The model is first partially validated by comparing computed results against experimental data on via test structures from planar ICs. Computed von Mises stresses show that the predicted failure agrees with the results of thermal cycle experiments. The model is then employed to study thermal stresses in interwafer Cu vias in 3D bonded IC structures. The results illustrate that there is a concern regarding the stability of interwafer Cu vias. Simulations show that the von Mises stresses in interwafer Cu vias decrease with decreasing pitch length at constant via size, increase with decreasing via size at constant pitch, and decrease with decreasing bonding thickness.