| 一种改进的Montgomery大数模乘器 |
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| 引用本文： | 苏斌,刘宏伟.一种改进的Montgomery大数模乘器[J].计算机工程与应用,2005,41(5):126-128. |
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| 作者姓名： | 苏斌 刘宏伟 |
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| 作者单位： | 北京科技大学信息学院计算机系,北京,100083;北京科技大学信息学院计算机系,北京,100083 |
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| 摘 要： | 文中针对Montgomery模乘算法进行了分析和改进,采用了一种理想的适合于硬件实现的Montgomery算法。根据此算法提出了一种新的脉动阵列结构,有效降低了芯片的面积,提高了模乘的运算速度。基于CMOS的0.6um工艺下,模乘器VLSI实现共用9k个等效门,最高工作时钟频率可达100MHz,完成1024位Montgomery模乘约需4295个时钟周期。
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| 关 键 词： | Montgomery算法 模乘器 脉动阵列 专用集成电路 |
| 文章编号： | 1002-8331-(2005)05-0126-03 |
An Improved Montgomery Algorithm for Modular Multiplier of Large Operands |
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| Su Bin,Liu Hongwei.An Improved Montgomery Algorithm for Modular Multiplier of Large Operands[J].Computer Engineering and Applications,2005,41(5):126-128. |
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| Authors: | Su Bin Liu Hongwei |
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| Abstract: | This paper analyzes and improves the algorithm of Montgomery.A novel systolic array modular multiplier is presented based on the modified Montgomery algorithm which is ideally suitable for hardware-inplementation.The modular multiplier effectively reduced its size and greatly increased its speed.Operating at maximum clock frequency up to 100MHz,it takes about 4295 clock cycles to accomplish a 1024-bit Montgomery modular multiplication.Using 0.6um CMOS technology,it holds about 9k gate counts. |
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| Keywords: | Montgomery algorithm modular multiplier systolic array ASIC |
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