Turbo码快速交织器的设计及其CPLD实现

针对目前Turbo码交织时延大影响编译码速率提升的缺陷，采用对m序列进行优选的方法设计了一种快速交织器，并基于CPLD给出硬件实现方案。仿真结果表明，该交织器在不增加编译码复杂度的情况下，一次迭代过程交织模块即能减少20％时间延迟．在时延和性能之间取得较好的折衷。

Design of a Fast Interleaver for Turbo Codes and Implementation Based on CPLD

This paper presents a fast interleaver based on the selected pseudo-random sequence with the shortest latency after analyzing the drawback of current interleavers that large interleave latency influence the advance of coding and decoding speed, and also presents the implementation based on CPLD. The analyzing results show that this interleaver could reduce the latency up to 20% during one iterative process without adding complexity. It achieves a tradeoff between the latency and the performance.