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Hardening silicon-on-insulator nMOSFETs by multiple-step Si+ implantation |
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| Affiliation: | 1. College of Information Engineering, Jimei University, Xiamen, Fujian 361021, People''s Republic of China;2. The State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, People''s Republic of China;1. School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China;2. BDS Electronics Co., Ltd., Bengbu 233010, China;1. Aix Marseille Univ, Univ Toulon, CNRS, IM2NP (UMR 7334), Marseille, France;2. STMicroelectronics, Crolles, France;3. Radiation Effects and Electrical Reliability (REER) Joint Laboratory, AMU-CNRS-ISEN-STMicroelectronics, France;1. Technion, Israel Institute of Technology, Haifa, Israel;2. TowerJazz, Migdal Haemek, Israel |
| Abstract: | A novel technique is proposed to improve total irradiation dose (TID) hardness of buried oxides in a 0.13 μm silicon-on-insulator (SOI) technology. Multiple-step Si ion implantation is implemented to avoid silicon film amorphization. Each implant step introduces silicon ion implantation of a lower dose into buried oxides which creates an amorphous/crystalline (a/c) interface inside the silicon layer. Rapid thermal annealing (RTA) removes implant-induced lattice damages by silicon recrystallization reflected in a/c interface moving towards the top silicon surface. The thermal process prevents top silicon layers from total amorphization arising in the technique of single high dose implantation method. X-ray Diffraction (XRD) spectrum confirms the existence of the a/c interface and determines the single implant dose. Experimental results on pseudo-MOS and H-gate partially-depleted SOI n-type MOSFETs show radiation tolerance up to 1.0 Mrad(Si) though introduced metastable electron traps lead to I–V hysteresis and bias instabilities. |
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