Carrier injection efficiency for the reliability study of 3.5–1.2 nm thick gate-oxide CMOS technologies

The hot carrier (HC) reliability has been investigated in MOSFETs with ultra-thin SiO₂ gate-oxide ranging from T_ox=3.5 to 1.2 nm and in high speed CMOS technologies in order to identify the worst-case of HC injections. Distinctions are obtained between the influence of the T_ox thinning and the shrink of the gate-length with L_G ranging from 0.25 to 0.1 μm. Results show that the worst-case of HC damage can be different from the bias condition of the maximum substrate current (IB) in N-channel devices and of the hot electron (HE) injections in P-channel devices with the T_ox and L_G margin. It is shown that the interface trap generation (ΔN_it) has become the main damage mechanism at long term with the use of the correlation between charge pumping analysis and drain current reduction. We focus on the hole injection efficiency, the extension of the degraded region (ΔL) with the L_G reduction and the influence of the carrier energy which all participate to the degradation of ultra-thin gate-oxide MOSFETs submitted to carrier injections.