| 基于Camera Link接口的高速视频图像采集系统 |
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| 引用本文： | 辛光泽,侯宏录,李飞,齐晶晶.基于Camera Link接口的高速视频图像采集系统[J].国外电子测量技术,2014(3):85-88. |
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| 作者姓名： | 辛光泽 侯宏录 李飞 齐晶晶 |
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| 作者单位： | 西安工业大学光电工程学院,西安710021 |
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| 基金项目： | 陕西省科学技术研究发展计划项目（2011K06-22） |
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| 摘 要： | 针对高速工业相机摄像过程中图像数据量大导致数据传输及存储困难的问题,提出了一种基于Camera Link接口的高速视频图像采集方案。Camera Link接口采用高级配置模式,并行传输8路像素数据、时钟信号及控制信号。现场可编程门阵列(FPGA)芯片生成图像采集模块及外围存储模块的时序控制逻辑。图像采集系统首先缓存像素数据于芯片内部FIFO,然后在SDRAM控制器的操作下将像素数据转移至8片同步动态随机存储器(SDRAM)中。实验结果表明,图像采集系统能够完成对分辨率1 280×1 024、帧频500f/s、位宽8bit高速视频图像的采集及存储。
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| 关 键 词： | FPGA Camera Link 图像采集 |
Image collection system based on Camera Link interface |
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| Xin Guangze Hou Honglu Li Fei Qi Jingjing.Image collection system based on Camera Link interface[J].Foreign Electronic Measurement Technology,2014(3):85-88. |
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| Authors: | Xin Guangze Hou Honglu Li Fei Qi Jingjing |
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| Affiliation: | Xin Guangze Hou Honglu Li Fei Qi Jingjing (School of Optoeleetronic Engineering, Xi＇ an Technological University, Xi ＇ an 710021, China) |
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| Abstract: | Image collection system based on Camera Link interface is designed to collect and store large amount ot oata in industrial camera shooting. Camera Link interface transmits 8 pixel data, pixel clock signal and control signal in full mode. FPGA chip generates the control logic of image acquisition module and external memory module, lmage collection system buffers pixel data in FIFO, and then transfers the data to 8 pieces of SDRAM. Experimental results show that the image collection system is able to collect and store 500 frames per second, the pixel of which is 1 280× 1 024. And the data width can be 8 bit. |
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| Keywords: | FPGA Camera Link image collectionl |
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