一种Viterbi译码算法的改进

提出了一种用寄存器交换法实现Viterbi译码的完整方案.采用一系列如截短法、用等效的思想简化启动过程、加比选计算并行化等方法,进一步改进了Viterbi译码算法的性能.使软判决位数、交织深度等参数在FPGA模拟时均可配置,并用Verilog硬件描述语言具体实现.基于Virtex5芯片进行综合,最大输出频率可达近200Mbps.利用Modelsim6.0和Haps-54开发板分别做了仿真和FPGA实验,同时搭建真实环境,进行BER性能测试,发现自研的IPCore在信噪比高于5.0时,优于Altera公司的同类产品和CDM-600,更适于深空卫星通信.

A Kind of Improved Viterbi Decoder

This paper presents one way to realize the register-exchanged based Viterbi decoder. A series of methods to further enhance the Viterbi decoding performance are adopted, such as path-cutted, equivalent startup process and parallelized ACS computing. Some parameters, such as soft-decision bits and the delay depth are adjustable in FPGA simulation. The decoder was implemented in Verilog HDL and synthesized on Virtex 5 FPGA. Results show that the maximal data output speed frequency is close to 200Mbps. Using Modelsim 6.0 and HAPS-54 board we made the simulation and FPGA experiments. When make the BER tests in the actual system, it comes to the conclusion that the IPCore of our own excels that of Altera and CMD-600, when the SNR is higher than 5.0. Thus, it more suits deep-space satellite communications.