A high‐speed MIMO FFT processor with full hardware utilization

The conventional way to design multi‐input‐multi‐output (MIMO) fast Fourier transform (FFT) processors for MIMO‐orthogonal frequency division multiplexing systems is to adopt a parallel architecture which uses as many single‐input‐single‐output FFT processors as the number of transmit/receive antennas. These MIMO FFT processors can provide high throughput, but they perform with low hardware utilization when there are not all input sequences available. In this paper, we propose a high‐speed MIMO FFT processor which can work efficiently with high throughput and full hardware utilization for variable 1 to 4 input sequences. Our MIMO FFT processor is designed by reordering and distributing data sequences to all data paths and is constructed by some novel modules. Being synthesized by using UMC 0.18‐μm process demonstrates that our 64‐point 4 × 4 FFT can achieve high throughput with full hardware utilization and perform correctly up to 62.25 MHz with low power consumption for variable 1 to 4 input sequences.