基于FPGA的数字跑表设计

Verilog程序通过综合、适配后形成配置文件,下载到FPGA器件中对FPGA进行配置,使FPGA成为实用的测频模块。通过波形仿真,符合本次设计的要求。最后,通过完整编译后的文件固化到开发板,接上高频信号源,实现了数字跑表的设计。本文详细介绍了数字跑表的设计指标,设计思路,设计方案,系统的电路设计,系统相应模块设计,系统硬件实现与测试结果。

Design of digital stopwatch based on FPGA

The Verilog program forms a configuration file after synthesis and adaptation,and then downloads it to THE FPGA device to configure FPGA,making FPGA into a practical frequency measurement module.Through waveform simulation,it conforms to the requirements of this design.Finally,the design of digital stopwatch is realized by solidifying the fully compiled file to the development board and connecting with the high frequency signal source.This paper introduces in detail the design index,design idea,design scheme,circuit design of the system,design of the corresponding module of the system,system hardware implementation and test results.