双FIFO的LBE总线与Avalon总线的接口系统设计

为了实现 LBE总线与 Avalon总线设备之间跨时钟域数据交换,设计了桥接在两种总线间的接口 IP 软核.利用Verilog硬件描述语言的层次化设计方法,设计了接口IP核的底层模块,其中包括命令FIFO模块、状态FIFO模块、LBE总线端接口模块和 Avalon总线端接口模块.在FPGA硬件平台上,进行两种总线间的双向数据传输实验.结果表明,采用双FIFO的 LBE总线与 Avalon总线接口系统满足设计要求,能够实现数据的稳定可靠交换.

Design of Interface System Between LBE Bus and Avalon Bus Based on Two FIFOs

In order to achieve the cross-clock domain data exchange between devices with LBE bus and Avalon bus,the interface IP soft core connected between the two buses is designed.The Verilog hardware is used to describe the hierarchical design method of language. The interface IP core module is designed,which including command FIFO module,state FIFO module,LBE interface module and Avalon interface module.In the FPGA hardware platform,two-way data transmission experiment between two buses is carried out.The results show that the interface system with two FIFOs between LBE bus and Avalon bus can exchange data steadily and reliably.