A novel nanoscale fin field effect transistor by amended channel: Investigation and fundamental physics

The present paper proposes a new Fin Field Effect Transistor (FinFET) with an amended Channel (AC). The fin region consists of two sections; the lower part which has a rounded shape and the upper part of fin as conventional FinFETs, is cubic. The AC-FinFET devices are proven to have a lower threshold voltage roll-off, reduced DIBL, better subthreshold slope characteristics, and a better gate capacitance in comparison with the C-FinFET. Moreover, the simulation result with three-dimensional and two-carrier device simulator demonstrates an improved output characteristic of the proposed structure due to reduction of self-heating effect. Due to the rounded shape of the lower fin region and decreasing corner effects there, the heat can flow easily, and the device temperature will decrease. Also the gate control over the channel increases due to the narrow upper part of the fin. The paper, thus, attempts to show the advantages of higher performance AC-FinFET device over the conventional one, and its effect on the operation of nanoscale devices.     

Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs

The gate induced drain leakage (GIDL) effect in negative capacitance (NC) FinFET is investigated. A Landau–Ginzburg–Devonshire equation (which considers the polarization gradient in ferroelectric material) is used to estimate the characteristics of the NC FinFET. Specifically, metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NC FinFETs are compared, in order to figure out the effect of the internal metal layer on the GIDL effect. To analyze the impact of the polarization gradient on the GIDL effect in NC FinFET, a polarization gradient coefficient is varied. For MFMIS, the polarization gradient doesn't significantly affect the device performance. The subthreshold swing improves but the GIDL effect deteriorates because of the “uniform” NC effect in channel region. For MFIS, the device performance is explicitly affected by the polarization gradient. Smaller polarization gradients result in non-uniform NC effect in channel region, resulting in severe GIDL effects. On the other hand, higher polarization gradients alleviate GIDL effects.     

Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Three-dimensional (3D) TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor (NMOS) transistor or P-channel metal-oxide semiconductor (PMOS) transistor can mitigate the cross section of single event upset (SEU) in 14-nm complementary metal-oxide semiconductor (CMOS) bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Unlike dual-interlock cell (DICE) design, this approach is more effective under heavy ion irradiation of higher LET, in the presence of enough taps to ensure the rapid recovery of well potential. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.     

Three-dimensional Monte Carlo simulation of bulk fin field effect transistor

In this paper,we investigate the performance of the bulk fin field effect transistor(FinFET) through a threedimensional(3D) full band Monte Carlo simulator with quantum correction.Several scattering mechanisms,such as the acoustic and optical phonon scattering,the ionized impurity scattering,the impact ionization scattering and the surface roughness scattering are considered in our simulator.The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work.Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.     

高k介质在新型半导体器件中的应用

当CMOS器件特征尺寸缩小到45 nm以下, SiO₂作为栅介质材料已经无法满足性能和功耗的需要, 用高 k材料替代SiO₂是必然选择. 然而, 由于高 k材料自身存在局限性, 且与器件其他部分的兼容性差, 产生了很多新的问题如界面特性差、 阈值电压增大、 迁移率降低等. 本文简要回顾了高 k栅介质在平面型硅基器件中应用存在的问题以及从材料、 结构和工艺等方面采取的解决措施, 重点介绍了高k材料在新型半导体器件中的应用, 并展望了未来的发展趋势.     

Effect of supply voltage and body-biasing on single-event transient pulse quenching in bulk fin field-effect-transistor process

Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor(Fin FET)technology. However, the studies of charge sharing induced single-event transient(SET) pulse quenching with bulk Fin FET are reported seldomly. Using three-dimensional technology computer aided design(3DTCAD) mixed-mode simulations,the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk Fin FET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing(RBB), the circuit with forward body-biasing(FBB) is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least.This can provide guidance for radiation-hardened bulk Fin FET technology especially in low power and high performance applications.     

14 nm FinFET和65 nm平面工艺静态随机存取存储器中子单粒子翻转对比

使用中国散裂中子源提供的宽能谱中子束流,开展14 nm FinFET工艺和65 nm平面工艺静态随机存取存储器中子单粒子翻转对比研究,发现相比于65 nm器件,14 nm FinFET器件的大气中子单粒子翻转截面下降至约1/40,而多位翻转比例从2.2%增大至7.6%,源于14 nm FinFET器件灵敏区尺寸(80 nm×30 nm×45 nm)、间距和临界电荷(0.05 fC)的减小.不同于65 nm器件对热中子免疫的现象,14 nm FinFET器件中M0附近10B元素的使用导致其表现出一定的热中子敏感性.进一步的中子输运仿真结果表明,高能中子在器件灵敏区中产生的大量的射程长、LET值大的高Z二次粒子是多位翻转的产生诱因,而单粒子翻转主要来自于p,He,Si等轻离子的贡献.     

Dependence of short channel length on negative/positive bias temperature instability (NBTI/PBTI) for 3D FinFET devices

A comprehensive study of the negative and positive bias temperature instability(NBTI/PBTI)of 3D FinFET devices with different small channel lengths is presented.It is found while with the channel lengths shrinking from 100 nm to 30 nm,both the NBTI characteristics of p-FinFET and PBTI characteristics of n-FinFET turn better.Moreover,the channel length dependence on NBTI is more serious than that on PBTI.Through the analysis of the physical mechanism of BTI and the simulation of 3-D stress in the FinFET device,a physical mechanism of the channel length dependence on NBTI/PBTI is proposed.Both extra fluorine passivation in the corner of bulk oxide and stronger channel stress in p-FinFETs with shorter channel length causes less NBTI issue,while the extra nitrogen passivation in the corner of bulk oxide induces less PBTI degradation as the channel length decreasing for n-FinFETs.The mechanism well matches the experimental result and provides one helpful guide for the improvement of reliability issues in the advanced FinFET process.     

Advanced quantitative analysis of epitaxial SiGe composition on production wafer for logic devices

Quantitative analyses of in situ boron‐doped SiGe composition on production wafers for 14 and 20‐nm logic devices were successfully characterized using advanced, small area Time‐of‐Flight Secondary Ion Mass Spectrometry analysis methods. The quantification of dopant levels in SiGe offered an improved method for tool‐to‐tool matching, process monitoring, and improvement, and performing this function accurately was necessary to enable advanced SiGe technology development that ensured world class manufacturing requirements were met. The boron concentration was measured with Time‐of‐Flight Secondary Ion Mass Spectrometry, based on a single Si_1‐xGe_x/Si on silicon substrate standard, which exhibited excellent matching with corresponding inline XRF intensity data. Time‐of‐Flight Secondary Ion Mass Spectrometry accurately characterized SiGe composition with adequate sensitivity to detect small boron concentration variations to fine‐tune process parameters. This provided insight to the relationship between overlap capacitance and Rodlin measurements with SiGe dopant levels and ultimately led to device performance improvement.     

Optical effects on the characteristics of GaAs nanoscale FinFET with vertical Gaussian doping profile

In this paper, the optical effects on the characteristics of GaAs FinFET with Gaussian doping profile in the vertical direction of the channel considering quantum mechanical effects (QME) have been theoretically examined and analyzed. The device characteristics are obtained using self-consistent solution of 3D Poisson–Schrödinger equations using interpolating wavelet method and Simpson's one-third rule. This method provides more accurate results by dynamically adjusting the computational mesh and scales the CPU time linearly with the number of mesh points using polynomial interpolation, hence reducing the numerical cost. The results obtained are compared with uniformly doped Si FinFET photodetector characteristics and used to examine the performance of the device for its suitable use as a photodetector in Opto-Electronic Integrated Circuit (OEIC) receivers.