Mechanics of stretchable batteries and supercapacitors

The last decade has witnessed fast developments and substantial achievements that have been shaping the field of stretchable electronics. Due to a persistent need of equally stretchable power sources, especially for some emerging bio-integrated applications enabled by this unusual class of electronics, stretchable energy storage systems have been attracting increasing attentions in the past few years. This article reviews the mechanics of stretchable batteries and supercapacitors that are enabled by novel structural designs of hard and soft components, involving four representative strategies (i.e., wavy, wrinkled design, origami design, serpentine bridge-island design, and fractal inspired bridge-island design). The key mechanics of each strategy is summarized, with focuses on the design concepts, unique mechanical behaviors, and analytical/computational models that guide the design optimization. Finally, some perspectives are provided on the remaining challenges and opportunities for future research.     

Removal of residual oxide layer formed during chemical–mechanical-planarization process for lowering contact resistance

In the present work, we report the formation of residual oxide layer during chemical–mechanical-planarization (CMP) process in the carbon nanotube (CNT) via interconnects and some feasible solutions for its removal. Residual oxide layer makes electrically poor contact between CNTs and metal resulting in high contact resistance in CNT via interconnects. We adopt post-CMP processes such as hydrofluoric acid (HF) or Ar plasma treatment to remove the residual oxide layer. X-ray photoelectron spectroscopy (XPS) was used to confirm the chemical state of samples before and after the post-CMP process. Silicon and oxygen peaks from silicon-based oxide layer observed after the CMP process were disappeared and reduced in its intensity by the post-CMP process, respectively. Furthermore, via resistance decreased more than 1 order of magnitude after the post-CMP process. It is found that the post-CMP process provides good electrical contact between CNTs and metal by removing the residual oxide layer.     

Oxidation behavior and electrical properties of metal interconnects with Ce-doped Ni–Mn spinel coatings

To improve the high-temperature oxidation resistance and electrical conductivity of ferritic stainless steels, protective Ce-doped NiMn₂O₄ spinel coatings were fabricated on the surface of SUS430 steel by electrophoretic deposition (EPD). The phase structure and microstructure of Ce-doped NiMn₂O₄ in both powder and coating forms were characterized using X-ray diffraction (XRD) and scanning electron microscopy (SEM). The high-temperature oxidation of the NiMn₂O₄ spinel coating before and after Ce doping in the air at 800 °C for 168 h was studied by weight gain experiments. The area-specific resistance (ASR) of coatings was measured by a standard four-probe method. It was found that the Ce-doped NiMn₂O₄ spinel powder displayed a stable structure, high crystallinity, fine grain size, and decreased agglomeration when the Ce content was fixed at 0.05 mol?L^?1. The oxidation kinetics of NiMn₂O₄-coated SUS430 steel before and after Ce doping obeyed a parabolic law with parabolic rate constants of 4.58 × 10^?15 g² cm^?4 s^?1 and 1.83 × 10^?15 g² cm^?4 s^?1, respectively. When oxidized at 800 °C for 50 h, the ASR value of the coated samples before and after Ce doping stabilized at about 15.2 mΩ?cm² and 14.5 mΩ?cm², respectively. This work demonstrated that the Ce-doped NiMn₂O₄ spinel coating improved the high-temperature oxidation resistance and the electrical conductivity of metal interconnects.     

FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects

The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line ＆ coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.     

Frequency properties of on-die power distribution network in VLSI circuits

The local voltage fluctuations in the supply and ground grids triggered by on-die logic cell switching in VLSI devices have been experimentally studied. The results show that these fluctuations have a resonant-like form i.e., the on-die power grid should be described as an RLC circuit. The studies reveal that the active element (i.e., CMOS logic cell) affects the frequency properties of power supply and ground grids during its switching (as opposed to before or after switching). It is demonstrated that the frequency properties of the both grids are inter-related via the interconnecting active elements.     

基于FDTD与SPICE的协同仿真分析方法

为了在进行高速电路的分析时能够发挥FDTD与SPICE各自的优势,提出一种将FDTD与SPICE相结合的协同仿真方法.该方法的特点是用FDTD来计算互连部分,而接在互连网络终端的元器件通过SPICE来计算,二者在元件与互连线相连接的端口上进行计算数据的通信.介绍了FDTD-SPICE方法的基本原理和计算流程,并以比较器电路为例详细讨论FDTD-SPICE协同仿真分析的方法的全过程.     

Conversion between standard and low-alpha lead in solder bumping production lines

Soft-errors caused by lead in solder-bumping have been a concern for many years. The problem is of special concern for high-density interconnection applications requiring solder to be placed directly over active circuitry. In that situation, alpha particles emitted by radioactive lead cause soft-errors with no possibility of shielding circuitry. For optimal cost-effectiveness, though, not all solder bumped wafers require low-alpha lead. MCNC has developed a solder bumping facility with both a research branch at MCNC and a full-scale production facility at its spin-off, Unitive Electronics Inc. We present results here of our work in incorporating low-alpha lead as part of our solder bumping process. We describe the amount of cross-contamination measured when alternating plating baths of regular lead and low-alpha lead.     

Barrier layers for Cu ULSI metallization

Barrier layers are integral parts of many metal interconnect systems. In this paper we review the current status of barrier layers for copper metallization for ultra-large-scale-integration (ULSI) technology for integrated circuits (ICs) manufacturing. The role of barrier layers is reviewed and the criteria that determine the process window, i.e. the optimum barrier thickness and the deposition processes, for their manufacturing are discussed. Various deposition methods are presented: physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), electroless deposition (ELD), and atomic layer CVD (ALCVD) for barrier layers implementation. The barrier integration methods and the interaction between the barrier and the copper metallization are presented and discussed. Finally, the common inspection and metrology for barrier layer are critically reviewed.     

RCE光电探测器顶部DBR的优化

对研制的 VCSEL 结构外延片制成的谐振腔增强型 (简称 RCE)光电探测器进行了物理分析和实验研究 ,由于 VCSEL 与 RCE光电探测器对谐振腔反射镜的反射率要求不同 ,通过腐蚀 VCSEL 器件顶部 DBR,改变顶镜反射率 ,能够得到量子效率峰值和半宽优化兼容的 RCE光电探测器 ,实现 VCSEL 与 RCE探测器的单片集成 .     

Textural and microstructural transformation of Cu damascene interconnects after annealing

Influence of annealing on the textural and microstructural transformation of Cu interconnects having various line widths is investigated. Two types of annealing steps have been considered here: room temperature over 6 months and 200°C for 10 min. The texture was determined by x-ray diffraction (XRD) of various cross-sectional profiles after electropolishing, and the surface, microstructure, and grain boundary character distribution (GBCD) of Cu interconnects were characterized using electron backscattered diffraction (EBSD) techniques. In order to analyze a relationship between the stress distribution and textural evolution in the samples, microstresses were calculated with decreasing line widths at 200°C using finite element modeling (FEM). In this investigation, it was found that the inhomogeneity of stress distribution in Cu interconnects is an important factor, which is necessary for understanding textural transformation after annealing. A new interpretation of textural evolution in damascene interconnects lines after annealing is suggested, based on the state of stress and the growth mechanisms of Cu electrodeposits.