Temperature-dependent ambipolar electrical characteristics of pentacene-based thin-film transistors: The impact of opposite-sign charge carriers

The temperature-dependent electrical and charge transport characteristics of pentacene-based ambipolar thin-film transistors (TFTs) were investigated at temperatures ranging from 77 K to 300 K. At room temperature (RT), the pentacene-based TFTs exhibit balanced and high charge mobility with electron (μ_e) and hole (μ_h) mobilities, both at about 1.6 cm²/V s. However, at lower temperatures, higher switch-on voltage of n-channel operations, almost absent n-channel characteristics, and strong temperature dependence of μ_e indicated that electrons were more difficult to release from opposite-signed carriers than that of holes. We observed that μ_e and μ_h both followed an Arrhenius-type temperature dependence and exhibited two regimes with a transition temperature at approximately 210–230 K. At high temperatures, data were explained by a model in which charge transport was limited by a dual-carrier release and recombination process, which is an electric field-assisted thermal-activated procedure. At T < 210 K, the observed activation energy is in agreement with unipolar pentacene-based TFTs, suggesting a common multiple trapping and release process-dominated mechanism. Different temperature-induced characteristics between n- and p-channel operations are outlined, thereby providing important insights into the complexity of observing efficient electron transport in comparison with the hole of ambipolar TFTs.     

High-performance 2,9-DPh-DNTT organic thin-film transistor by weak epitaxy growth method

2,9-DPh-DNTT, an isomeric of diphenyl-dinaphtho[2,3-b:2′,3′-f]-thieno[3,2-b] thiophene (DPh-DNTTs), is an emerging candidate of high mobility organic semiconductor material. In this work, a high performance 2,9-DPh-DNTT organic thin-film transistor (OTFT) is fabricated by the method of weak epitaxy growth. The quality of 2,9-DPh-DNTT thin film was significantly improved when its epitaxial layer grows on an inducing layer of para-sexiphenyl (p-6P). Continuous large-area, highly ordered and terraced 2,9-DPh-DNTT polycrystalline thin films are obtained. The hole mobility of as-fabricated 2,9-DPh-DNTT thin-film transistor reaches up to 6.4 cm² V⁻¹s⁻¹. This simple process of preparing high mobility 2,9-DPh-DNTT thin-film transistor supplies a facile route of large-area OTFT fabrication.     

Organic photodetector with built-in amplification for the detection of visible light with low optical power

We report on an organic-based photodetector that integrates a dual-gate organic thin-film transistor (DG-OTFT) with an organic photodiode (OPD) to produce a device with a high effective responsivity at low optical power and video-rate compatible response. In this device, the OPD operates in photovoltaic mode, instead of the commonly used photoconductive mode, to modulate one of the gate voltages of the DG-OTFT. Effective responsivity values of 10 A W⁻¹ are measured at optical power values lower than 10 nW at 635 nm. Modeling of the operation of this new photodetector suggests that effective responsivity values up to 10⁵ A W⁻¹ can be achieved at optical powers of 1 nW using current printing technology and state-of-the-art organic semiconductors.     

格列齐特脂质体的制备及质量评价

采用薄膜分散法制备格列齐特脂质体,以粒径和包封率为考核指标,通过单因素实验和正交实验优化制备条件,测定最优条件制备格列齐特脂质体的平均粒径和包封率。确定最优制备条件为:药脂比1∶10(g∶g)、超声时间10min、成膜温度60℃、缓冲液pH值6。所制备脂质体的平均粒径为(108.3±12.4)nm、包封率为(72.19±3.6)%、平均Zeta电位为(-40.8±2.3)mV,且在4℃下保存稳定性好。电镜照片显示,所制备脂质体圆整度好、粒径均一、无粘连。表明采用薄膜分散法制备格列齐特脂质体工艺稳定,质量可控。     

Numerical investigation of a double-junction a:SiGe thin-film solar cell including the multi-trench region

We present a new approach based on the multi-trench technique to improve the electrical performances, which are the fill factor and the electrical efficiency. The key idea behind this approach is to introduce a new multi-trench region in the intrinsic layer, in order to modulate the total resistance of the solar cell. Based on 2-D numerical investigation and optimization of amorphous SiGe double-junction (a-Si:H/a-SiGe:H) thin film solar cells, in the present paper numerical models of electrical and optical parameters are developed to explain the impact of the multi-trench technique on the improvement of the double-junction solar cell electrical behavior for high performance photovoltaic applications. In this context, electrical characteristics of the proposed design are analyzed and compared with conventional amorphous silicon double-junction thin-film solar cells.     

Physical modification of polymeric support layer for thin film composite forward osmosis membranes by metal–organic framework-based porous matrix membrane strategy

Physical modification of support layers (SLs) for thin-film composite (TFC) forward osmosis (FO) membranes is the main goal of this study. Accordingly, the strategy of metal–organic framework (MOF)-based porous matrix membrane (PMM) was used for the fabrication of controllable SLs. Fourteen different TFC FO membranes were successfully fabricated by interfacial polymerization (IP) technique over the fourteen different SLs made of polyetherimide (PEI), polyethersulfone (PES), and twelve MOF-based PMM. The controllable MOF particles, fabricated SLs, and TFC membranes were characterized by Fourier-transform infrared spectroscopy (FTIR), powder X-ray diffraction (PXRD), dynamic light scattering (DLS), field emission scanning electron microscopy (FESEM), X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), contact angle (CA), inductively coupled plasma (ICP), and developed SHN1 method. The results showed that the PMM strategy can lead to an increase in the degree of crosslinking of polyamide (PA) as a result of physical modification of the original SLs. Also, the PMM strategy reduced the structural parameters and hence the internal concentration polarization (ICP) was controlled. However, according to the characteristic curve, physical modification of the structure of PES and PEI by MOF-based PMM strategy caused a small and dramatic effect (respectively) on the performance of the TFC FO membranes. © 2019 Wiley Periodicals, Inc. J. Appl. Polym. Sci. 2019 , 137, 48672.     

Synergistic Improvement of Long-Term Plasticity in Photonic Synapses Using Ferroelectric Polarization in Hafnia-Based Oxide-Semiconductor Transistors

A number of synapse devices have been intensively studied for the neuromorphic system which is the next-generation energy-efficient computing method. Among these various types of synapse devices, photonic synapse devices recently attracted significant attention. In particular, the photonic synapse devices using persistent photoconductivity (PPC) phenomena in oxide semiconductors are receiving much attention due to the similarity between relaxation characteristics of PPC phenomena and Ca²⁺ dynamics of biological synapses. However, these devices have limitations in its controllability of the relaxation characteristics of PPC behaviors. To utilize the oxide semiconductor as photonic synapse devices, relaxation behavior needs to be accurately controlled. In this study, a photonic synapse device with controlled relaxation characteristics by using an oxide semiconductor and a ferroelectric layer is demonstrated. This device exploits the PPC characteristics to demonstrate synaptic functions including short-term plasticity, paired-pulse facilitation (PPF), and long-term plasticity (LTP). The relaxation properties are controlled by the polarization of the ferroelectric layer, and this polarization is used to control the amount by which the conductance levels increase during PPF operation and to enhance LTP characteristics. This study provides an important step toward the development of photonic synapses with tunable synaptic functions.     

Design of high speed gate driver employing IZO TFTs

This paper presents a new bi-side gate driver integrated by indium-zinc-oxide thin film transistors (IZO TFTs). Our optimized operate method can achieve high speed performance by employing a lower duty ratio (25%) CK2 with its pulse located in the middle of the pulse of CK2L to fully use the bootstrapped high voltage of node Q. In addition, the size of devices is optimized by calculation and simulation, and the function of the proposed gate driver is predicted by the circuit simulation. Furthermore, the proposed gate driver with 20 stages is fabricated by the IZO TFTs process. It is shown that a 2.6 μs width pulse with good noise-suppressed characteristic can be successfully output at the condition of R_load = 6 kΩ and C_load = 150 pF. The power consumption of the proposed gate driver with 20 stages is measured as 1 mW. Hence, the proposed gate driver may be applied to the display of 4K resolution (4096 × 2160) at a frame rate of 120 Hz. Moreover, there is a good stability for the proposed gate driver under 48 h operation.