THE effect of Srandom DOPANT fluctuation on threshold voltage and drain current variation in junctionless nanotransistors

We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation (10000 randomizations). With this simulation, we could study the effects of varying the dimensions (length and width), and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region (off) and overthreshold (on). It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion (compared with that of the subthreshold). These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel.     

Controlling thickness to tune performance of high-mobility transparent conducting films deposited from Ga-doped ZnO ceramic target

Structure modification has been found to tune significantly the transparent-conducting performance, especially mobility and conductivity of hydrogenated Ga-doped ZnO (HGZO) films. The strong correlation between film thickness and mobility of the films is revealed. The mobility increases quickly with increasing the thickness from 350 to 900 nm, and then tends to be saturated at further thicknesses. A higher mobility than 50 cm²/Vs can be achieved, which is an extra-high value for polycrystalline ZnO films deposited by using the sputtering technique. The thickness-dependent mobility originates from scatterings on grain boundaries and dislocation-induced defects controlled by thin-film growth. Based on the Volmer-Weber model, an expansion model is built up to describe the thickness-dependent crystal growth of the HGZO films, especially at the thick films. As a result, the 800 nm-thick HGZO film obtains the highest performance with high mobility of 51.5 cm²/Vs, low resistivity of 5.3 × 10^?4 Ωcm, and good transmittance of 83.3 %.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

Using d-limonene as the non-aromatic and non-chlorinated solvent for the fabrications of high performance polymer light-emitting diodes and field-effect transistors

Aiming to environment protection, green solvents are crucial for commercialization of solution-processed optoelectronic devices. In this work, d-limonene, a natural product, was introduced as the non-aromatic and non-chlorinated solvent for processing of polymer light-emitting diodes (PLEDs) and organic field effect transistors (OFETs). It was found that d-limonene could be a good solvent for a blue-emitting polyfluorene-based random copolymer for PLEDs and an alternating copolymer FBT-Th₄(1,4) with high hole mobility (μ_h) for OFETs. In comparisons to routine solvent-casted films of the two conjugated polymers, the resulting d-limonene-deposited films could show comparable film qualities, based on UV–vis absorption spectra and observations by atomic force microscopy (AFM). With d-limonene as the processing solvent, efficient blue PLEDs with CIE coordinates of (0.16, 0.16), maximum external quantum efficiency of 3.57%, and luminous efficiency of 3.66 cd/A, and OFETs with outstanding μ_h of 1.06 cm² (V s)⁻¹ were demonstrated. Our results suggest that d-limonene would be a promising non-aromatic and non-chlorinated solvent for solution processing of conjugated polymers and molecules for optoelectronic device applications.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

半导体传感器在生物分析科学中的应用(英文)

回顾了半导体生化传感器 (ISFET 和 LA PS)在医学监测、免疫检测、免疫分析、D N A 杂交以及细胞培养等方面应用的进展。为使半导体器件适用于生化检测,对其中所采用的检测手段和取得的研究结果进行了分析。展望了通过与微流体网络相结合,基于半导体传感器的实验室芯片化的可行性。     

Measurement and Identification of the Parameters of SPICE-Models of a Bipolar Transistor

A method of measuring and identifying the static parameters of a bipolar transistor is considered. The characteristic of the transistor, from which the parameters of the model are determined, is chosen depending on what group the calculated parameters belong to. The characteristics are measured in such a way that the equations of the model describing them can be reduced to the simplest form.     

铁电存储场效应晶体管I-V特性的物理机制模拟

文章讨论的模型主要描述了铁电存储场效应晶体管（FEMFET）的I-V特性。从理论结果可反映出几何尺寸效应和材料参数对晶体管电特性的影响。传统的阈值电压的概念巳不再适用，由于铁电层反偏偶极子的开关作用，自发极化的增加对存储器的工作状态产生很小的影响。该模型可用于设计和工艺参数的优化，并由直观原型的方法得到了验证。     

大功率晶体管的保护电路

大功率晶体管调速系统中作为开关元件使用时，共优点是开关频率比可控硅的高，但是不注意保护就容易损坏。着重研究过电流故障，并对保护作用的影响进行了分析，进而提出了防止过电流的方法和工作原理。     

浅谈低频小功率三极管的输入电阻的计算

就低频小功率三极管的输入电阻的计算进行了探讨。