应用于GSM/EDGE零中频接收机的CMOS射频前端

介绍了一个零中频接收机CMOS射频前端,适用于双带(900MHz/1800 MHz)GSM/EDGE;E系统.射频前端由两个独立的低噪声放大器和正交混频器组成,并且为了降低闪烁噪声采用了电流模式无源混频器.该电路采用0.13 μm CMOS工艺流片,芯片面积为0.9 mm×1.0 mm.芯片测试结果表明:射频前端在90...     

一种基于开关电容的可配置多模滤波器

设计了一种基于开关电容的可配置多模滤波器,由模拟信号处理模块、数字控制模块和参考电压电流源组成;通过数字控制模块配置滤波器工作在旁路、低通、带通、自适应工作状态,同时实现低通滤波器截止频率和带通滤波器中心频率可调;自适应滤波器截止频率和中心频率能准确跟随输入信号主频率.整个电路基于SMIC 0.18μm CMOS工艺实...     

A low spur,low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop(PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs(1 kHz to 10 MHz);the phase noise is-89 ...     

一种用于G类音频功放的带自适应输出的双模电荷泵

本文设计了一种给G类音频功率放大器提供自适应电源的双模电荷泵电路。根据输入信号的幅度,该电荷泵可以提供两档电压轨来节省功耗。它在重载下工作于电流控制模式,轻载下工作于脉冲频率调制(PFM)模式来降低功耗。在PFM工作模式下,引入功率管尺寸动态调整的技术来减小PFM模式下的输出电压纹波并防止开关频率进入音频范围。该电荷泵电路采用0.18μm,3.3V的CMOS工艺制备。试验结果表明该电荷泵在1/2x模式下可以实现79.5％的最高效率,在1x模式下可以实现83.6％的最高效率。在PFM控制模式下,电荷泵在负载电流小于120mA的范围内,其输出纹波小于15mV;在电流控制模式下,在负载电流小于300mA的范围内,其纹波小于18mV。测试结果与文中提出的功率分段的PFM控制模式的纹波、效率的解析模型得到的计算及仿真结果基本一致,验证了模型与分析方法的正确性。     

一种8.75-11.2 GHz适用于802.11a/b/g零中频收发机系统低噪声分数频率综合器

介绍了一种适用于802.11a/b/g零中频接收机的超宽带分数频率综合器。文章详细推导了分数频率综合器相位噪声和杂散的数学模型,并给出了降低噪声和杂散的优化方法。实验结果表明,输出频率二分频后,在4.375GHz时积分噪声低于1度（1kHz 到100MHz);参考频率33-MHz处杂散低于-60dBc。芯片基于标准0.13微米RF CMOS工艺,电路工作电压1.2V,功耗39.6mW。     

用于WCDMA的高线性，高增益精度的直接变频发射机

本文描述了一个高线性,高输出功率的直接变频发射机。该发射机针对宽频码分多工存取标准设计,在0.13微米CMOS工艺下实现。本系统最大输出功率为6.8dBm,消耗的电流为38mA。在最大输出功率下,邻道功率泄漏（ACLR）和载波泄漏分别为-44dBc@5MHz和-37dBc,相应的误差矢量振幅（EVM）为3.6%。整个系统可以以6dB为步长实现66dB的增益控制范围,通过电阻阵列的微调功能,增益控制精度可以达到0.1dB以内。系统的镜像抑制比可以在整个输出范围内保持在-47dBc以下。     

CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm~2.     

采用balun低噪声放大器的5GHz 7.2-dB NF低功耗直接转换接收机前端电路

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm². It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

A dual-mode analog baseband with digital-assisted DC-offset calibration for WCDMA/GSM receivers

A dual-mode analog baseband with digital-assisted DC-offset calibration(DCOC) for WCDMA/GSM receiver is presented.A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC-offset component only.This method has no bandwidth sacrifice.After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm.The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz.Total baseband gain can be programmed from 6 to 54 dB.The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm~2.     

一种快速捕获、带宽可调的锁相环电路

设计实现了一个快速捕获,带宽可调的电荷泵型锁相环电路。采用了一种利用状态机拓展鉴频鉴相器检测范围的方法,加快了环路的锁定;通过SPI总线实现电荷泵电流配置和调整VCO延时单元的延迟时间,优化了电路性能。芯片采用中芯国际0.18μmCMOS工艺,测试结果表明,锁相环锁定在100MHz时的抖动均方值为24ps,偏离中心频率1MHz处的相位噪声为-98.62dBc/Hz。