Assessment of sperm count in rural population of central India

26 clinician trainees' recollections of experiences in a diagnostic preschool program were analyzed in terms of strength and weaknesses of the program.     

High resistivity In-doped ZnTe: electrical and optical properties

Semi-insulating <111> ZnTe prepared by In doping during Bridgman growth was found to have a resistivity of 5.74 × 10⁷ ohm-cm, the highest reported so far in ZnTe, with hole concentration of 2.4 × 10⁹/cm³ and hole mobility of 46 cm² /V.s at 300 K. The optical band gap was 2.06 eV at 293 K compared with 2.26 eV for undoped semiconducting ZnTe. Thermally stimulated current (TSC) studies revealed 2 trap levels at depths of 202–222 meV and 412–419 meV, respectively. Photoluminescence (PL) studies at 10 K showed strong peaks at 1.37 eV and 1.03 eV with a weak shoulder at 1.43 eV. Short anneal for 3 min at 250°C led to conversion to a p-type material with resistivity, 14.5 ohm-cm, indicating metastable behaviour. Raman studies carried out on undoped and In-doped samples showed small but significant differences. Possible models for semi-insulating behaviour and meta-stability are proposed.     

Analysis of Fatty Acid and Lignan Composition of Indian Germplasm of Sesame to Evaluate Their Nutritional Merits

An attempt was made to individually analyze a germplasm collection of 54 indigenous Indian sesame cultivars for fatty acid and lignan composition of their seed oil by gas chromatography and high performance liquid chromatography, respectively. The entries varied in their fatty acid and lignan composition. The mean percentage contents of palmitic, stearic, oleic, linoleic and α‐linolenic acids ranged between 10–22, 5–10, 38–50, 18–43 and less than 1 whereas sesamol, sesamin and sesamolin scored between 3–37, 27–67, 20–59 of the total percentage of lignan, respectively. The highest percentage of α‐linolenic acid (ALA) was obtained in Var‐9 (1.3 % of the total fatty acids). Among the lignans, high sesamin content is considered to be significant, particularly in terms of long shelf life and nutraceutical value of sesame seed oil. The study has broadened our understanding related to differential biochemical composition of the rich sesame germplasms, thereby providing us with a useful groundwork for identifying potential targets and suitable cultivars for genetic engineering approaches to be undertaken in order to improve the nutritional quality of sesame oil, which in turn would be beneficial towards human health.     

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes that reduce this redundant switching incur considerable overhead in terms of delay, power, and area. This paper presents novel operand isolation techniques based on supply gating that reduce overheads associated with isolating circuitry. The proposed schemes also target leakage minimization and additional operand isolation at the internal logic of datapath to further reduce power consumption. We integrate the proposed techniques and power/delay models to develop a synthesis flow for low-power datapath synthesis. Simulation results show that the proposed operand isolation techniques achieve at least 40% reduction in power consumption compared to original circuit with minimal area overhead (5%) and delay penalty (0.15%)     

Instability of plane compressible gas sheets

Summary The instability of a plane compressible gas sheet in a quiescent viscous liquid medium of infinite expanse has been studied. It is found that there exist two unstable modes of disturbances, sinuous and varicose. For temporal instability, sinuous disturbance is stable if the gas Weber number, defined as the ratio of aerodynamic to capillary forces, is less than unity, varicose mode controls the instability process except for large Weber numbers when both modes become equally important, and gas compressibility effect always enhances instability development and induces an additional range of unstable wave numbers. For spatial-temporal evolution of disturbances, it is found that convective instability does not exist at all and the instability of plane gas sheets is always absolute in nature, which is strikingly opposite to the instability of plane liquid sheets. The absolutely unstable disturbance is found always temporally growing, although it may be spatially growing or decaying depending on flow conditions. Gas compressibility always enhances and liquid viscosity damps out both the temporal and the spatial part of absolute instability growth rate. Although the Weber number always promotes the temporal growth rate of absolute instability, it has a dual effect of enhancing and inhibiting the spatial growth rate.     

Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies

Dual-V_t design technique has proven to be extremely effective in reducing subthreshold leakage in both active and standby mode of operation of a circuit in submicrometer technologies. However, aggressive scaling of technology results in different leakage components (subthreshold, gate and junction tunneling) to become significant portion of total power dissipation in CMOS circuits. High-V_t devices are expected to have high junction tunneling current (due to stronger halo doping) compared to low-V_t devices, which in the worst case can increase the total leakage in dual-V_t design. Moreover, process parameter variations (and in turn V_t variations) are expected to be significantly high in sub-50-nm technology regime, which can severely affect the yield. In this paper, we propose a device aware simultaneous sizing and dual-V_t design methodology that considers each component of leakage and the impact of process variation (on both delay and leakage power) to minimize the total leakage while ensuring a target yield. Our results show that conventional dual-V_t design can overestimate leakage savings by 36% while incurring 17% average yield loss in 50-nm predictive technology. The proposed scheme results in 10%-20% extra leakage power savings compared to conventional dual-V_t design, while ensuring target yield. This paper also shows that nonscalability of the present way of realizing high-V_t devices results in negligible power savings beyond 25-nm technology. Hence, different dual-V_t process options, such as metal gate work function engineering, are required to realize high-performance and low-leakage dual-V_t designs in future technologies.     

Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation

This paper presents a novel design methodology for ultralow-power design using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of millihertz). Standard design techniques suitable for super-threshold design can be used in the subthreshold region. However, in this study, it has been shown that a complete co-design at all levels of hierarchy (device, circuit, and architecture) is necessary to reduce the overall power consumption while achieving acceptable performance (hundreds of millihertz) in the subthreshold regime of operation. Simulation results of co-design on a five-tap finite-impulse-response filter shows /spl sim/2.5/spl times/ improvement in throughput at iso-power compared to a conventional design.     

Low-power scan design using first-level supply gating

Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement the masking effect by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops. The supply gating transistor is turned off in the scan-in mode, essentially gating the supply. Adding an extra transistor in only one logic level renders significant advantages with respect to area, delay, and power overhead compared to existing methods, which use gating logic at the output of scan flip-flops. Moreover, the proposed gating technique allows a reduction in leakage power by input vector control during scan shifting. Simulation results on ISCAS89 benchmarks show an average improvement of 62% in area overhead, 101% in power overhead (in normal mode), and 94% in delay overhead, compared to the lowest cost existing method.