Variational density matrix approach to the temperature-dependent elementary excitation spectrum of two-dimensional liquid4He

Using the variational density matrix method, we obtain a temperature-dependent elementary excitation spectrum for two-dimensional liquid⁴He. For more precise results, we use a Jastrow-Feenberg-type trial wave function and include the contribution of elementary diagrams within the hypernetted chain approximation. The behavior of the excitation spectrum as a function of the temperature and density in two dimensions is similar to that of the bulk system, but has a smaller roton minimum. The roton minimum of the excitation spectrum decreases with increasing temperature and increases with increasing density at low densities but decreases at large densities. The results agree well with Monte Carlo calculations and are closer than pevious theories to experimental measurements of⁴He film adsorbed on substrates.     

PathRank: Ranking nodes on a heterogeneous graph for flexible hybrid recommender systems

We present a flexible hybrid recommender system that can emulate collaborative-filtering, Content-based Filtering, context-aware recommendation, and combinations of any of these recommendation semantics. The recommendation problem is modeled as a problem of finding the most relevant nodes for a given set of query nodes on a heterogeneous graph. However, existing node ranking measures cannot fully exploit the semantics behind the different types of nodes and edges in a heterogeneous graph. To overcome the limitation, we present a novel random walk based node ranking measure, PathRank, by extending the Personalized PageRank algorithm. The proposed measure can produce node ranking results with varying semantics by discriminating the different paths on a heterogeneous graph. The experimental results show that our method can produce more diverse and effective recommendation results compared to existing approaches.     

Limitations and challenges of computer-aided design technology forCMOS VLSI

As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full potential of available transistors and interconnect is increasingly important. Design technology (DT) is concerned with the automated or semi-automated conception, synthesis, verification, and eventual testing of microelectronic systems. While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design technology faces fundamental limitations inherent in the computational intractability of design optimizations and in the broad and unknown range of potential applications within various design processes. In this paper, we explore limitations to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density performance, and power dissipation     

Toward better wireload models in the presence of obstacles

Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probability function that assigns a probability to each of these paths to be occupied by a wire. In this paper, we apply a generating polynomial technique to derive complete expressions for site density functions which take effects of layout region aspect ratio and the presence of obstacles into account. The effect of an obstacle is separated into two parts: the terminal redistribution effect and the blockage effect. The layout region aspect ratio and the obstacle area are observed to have a much larger effect on the wirelength distribution than the obstacle's aspect ratio and location. Accordingly, we suggest that these two parameters be included as indices of lookup tables in wireload models. Our results apply to a priori wirelength estimation schemes in chip planning tools to improve parasitic estimation accuracy and timing closure; this is particularly relevant for system-on-chip designs where IP blocks are combined with row-based layout     

4He Binding Energies on Single-Wall Carbon Nanotube Bundles

We have measured the temperature-programmed desorption spectrum of ⁴ He atoms from a sample of Single-Wall Carbon Nanotubes with various initial coverages. Several Analysis techniques have been applied to the data and the results are reported here.     

“Multipoint Force Feedback” Leveling of Massively Parallel Tip Arrays in Scanning Probe Lithography

Nanoscale patterning with massively parallel 2D array tips is of significant interest in scanning probe lithography. A challenging task for tip‐based large area nanolithography is maintaining parallel tip arrays at the same contact point with a sample substrate in order to pattern a uniform array. Here, polymer pen lithography is demonstrated with a novel leveling method to account for the magnitude and direction of the total applied force of tip arrays by a multipoint force sensing structure integrated into the tip holder. This high‐precision approach results in a 0.001° slope of feature edge length variation over 1 cm wide tip arrays. The position sensitive leveling operates in a fully automated manner and is applicable to recently developed scanning probe lithography techniques of various kinds which can enable “desktop nanofabrication.”