Temporal-logic query checking over finite data streams

International Journal on Software Tools for Technology Transfer - This paper describes a technique for solving temporal-logic queries over finite sets of finite-length data streams. Such data...     

Identification of a novel inhibitor (NSC 665564) of dihydroorotate dehydrogenase with a potency equivalent to brequinar

A novel inhibitor of dihydroorotate dehydrogenase (DHO-DH) has been discovered using data from the National Cancer Institute's in vitro drug screen. Upon analysis of cytotoxicity results from the sixty tumor cell lines used in this screen, the COMPARE program predicted that NSC 665564 was likely to have the same mechanism of inhibition as brequinar, a known potent inhibitor of DHO-DH. We validated this prediction experimentally using MOLT-4 lymphoblast and found the IC50 of brequinar (0.5 microM) and NSC 665564 (0.3 microM) were comparable and that this induced cytotoxicity was reversed by either uridine or cytidine. The enzyme target of NSC 665564 was shown to be identical to that of brequinar when incubation with each drug followed by a 1 h pulse with [14C] sodium bicarbonate resulted in cellular accumulation of [14C]N-carbamyl-L-aspartic acid and [14C]L-dihydroorotic acid, with concurrent marked depletion of CTP and UTP. The Ki's for NSC 665564 and brequinar were 0.14 and 0.24 microM, respectively, when partially purified MOLT-4 mitochondria (the site of DHO-DH) were used. These results show that mechanistic predictions obtained using correlations from the COMPARE algorithm are independent of structure since the structure of NSC 665564 is dissimilar to that of other established DHO-DH inhibitors.     

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A linear-time model-checking algorithm for the alternation-free modal mu-calculus

We develop a model-checking algorithm for a logic that permits propositions to be defined using greatest and least fixed points of mutually recursive systems of equations. This logic is as expressive as the alternation-free fragment of the modal mu-calculus identified by Emerson and Lei, and it may therefore be used to encode a number of temporal logics and behavioral preorders. Our algorithm determines whether a process satisfies a formula in time proportional to the product of the sizes of the process and the formula; this improves on the best known algorithm for similar fixed-point logics.     

Local model checking and protocol analysis

This paper describes a local model-checking algorithm for the alternation-free fragment of the modal mu-calculus that has been implemented in the Concurrency Factory and discusses its application to the analysis of a real-time communications protocol. The protocol considered is RETHER, a software-based, real-time Ethernet protocol developed at SUNY at Stony Brook. Its purpose is to provide guaranteed bandwidth and deterministic, periodic network access to multimedia applications over commodity Ethernet hardware. Our model-checking results show that (for a particular network configuration) RETHER makes good on its bandwidth guarantees to real-time nodes without exposing non-real-time nodes to the possibility of starvation. Our data also indicate that, in many cases, the state-exploration overhead of the local model checker is significantly smaller than the total amount that would result from a global analysis of the protocol. In the course of specifying and verifying RETHER, we also identified an alternative design of the protocol that warranted further study due to its potentially smaller run-time overhead in servicing requests for data transmission. Again, using local model checking, we showed that this alternative design also possesses the properties of interest. This observation points out one of the often-overlooked benefits of formal verification: by forcing designers to understand their designs rigorously and abstractly, these techniques often enable the designers to uncover interesting design alternatives.     

Pragmatics of model checking: an STTT special section

Since its discovery in the early 1980s, model checking has emerged as one of the most exciting areas in the field of formal verification of system correctness. The chief reason for this enthusiasm resides in the fact that model checkers establish in a fully automated manner whether or not a system satisfies formal requirements; users need not construct proofs. Until the early 1990s, however, the practical impact of model checking was modest, in large part because the state-explosion problem limited the applicability of the technology. Recent advances in the field have dramatically expanded the scope of model checking, however, and interest in it on the part of practitioners is growing. This special section surveys several recent approaches to attacking the state explosion that are supporting the continued advancement of model checking as a viable technology for improved system design.     

Control of vocal repertoire by reward in budgerigars (Melopsittacus undulatus).

The calls of some bird species may be modified by reward and punishment. However, the operant control of vocal topographies (i.e., the effect of reward or punishment on the physical dimensions of a vocal response) in such species has not been extensively explored. Using a computer-based, real-time system for rewarding vocalizations with food, the authors placed 3 budgerigars under a frequency-dependent reward schedule. During a session, the budgerigars received food for each vocalization that differed from the last N rewarded vocalizations. It was found that each of the budgerigars adapted their vocalizations to this procedure. When the value of N was 1 or 2, the birds "solved" the frequency-dependent schedule by developing N ?+?1 call types and used a simple "win stay, lose switch" sequencing strategy. At N?=?3, 1 of the birds again produced N ?+?1 (i.e., 4) call types, and another solved the criterion by markedly increasing call variability. New calls developed from the elements of old call types and using multidimensional scaling techniques, the authors traced the evolution of each new call type from the previous experimental call repertoire. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Triggered Message Sequence Charts

This paper introduces triggered message sequence charts (TMSCs), a graphical, mathematically well-founded framework for capturing scenario-based system requirements of distributed systems. Like message sequence charts (MSCs), TMSCs are graphical depictions of scenarios, or exchanges of messages between processes in a distributed system. Unlike MSCs, however, TMSCs are equipped with a notion of trigger that permits requirements to be made conditional, a notion of partiality indicating that a scenario may be subsequently extended, and a notion of refinement for assessing whether or not a more detailed specification correctly elaborates on a less detailed one. The TMSC notation also includes a collection of composition operators allowing structure to be introduced into scenario specifications so that interactions among different scenarios may be studied. In the first part of this paper, TMSCs are introduced and their use in support of requirements modeling is illustrated via two extended examples. The second part develops the mathematical underpinnings of the language     

Distributed prototyping from validated specifications

We present vpl2cxx, a translator that automatically generates efficient, fully distributed C++ code from high-level system models specified in the mathematically well-founded VPL design language. As the Concurrency Workbench of the New Century (CWB-NC) verification tool includes a front-end for VPL, designers may use the full range of automatic verification and simulation checks provided by this tool on their VPL system designs before invoking the translator, thereby generating distributed prototypes from validated specifications. Besides being fully distributed, the code generated by vpl2cxx is highly readable and portable to a host of execution environments and real-time operating systems (RTOSes). This is achieved by encapsulating all generated code dealing with low-level interprocess communication issues in a library for synchronous communication, which in turn is built upon the adaptive communication environment (ACE) client-server network programming interface. Finally, example applications show that the performance of the generated code is very good, especially for prototyping purposes. We discuss two such examples, including the RETHER real-time Ethernet protocol for voice and video applications.     

Verification of an active control system using temporal process algebra

In this paper we describe complementary approaches that can be used to ensure the reliability of real-time systems, such as those used in active structural control systems. These approaches include both model-checking and simulation, and are based on a temporal process algebra. We combine these formal methods with a high-level, graphical modeling technique, Modechart, to specify an active structural control system consisting of several processors. Timing requirements on the system are specified and verified with a combination of process algebraic models and modal logic, and various simulation concepts are described for debugging models and for gaining insight into system behavior.