Dynamic replication factor model for Linux containers-based cloud systems

The Journal of Supercomputing - Infrastructure-as-a-service container-based virtualization is gaining interest as a platform for running distributed applications. With increasing scale of cloud...     

FPGA implementations of fast Fourier transforms for real-time signal and image processing

Applications based on the fast Fourier transform (FFT), such as signal and image processing, require high computational power, plus the ability to experiment with algorithms. Reconfigurable hardware devices in the form of field programmable gate arrays (FPGAs) have been proposed as a way of obtaining high performance at an economical price. However, users must program FPGAs at a very low level and have a detailed knowledge of the architecture of the device being used. They do not therefore facilitate easy development of, or experimentation with, signal/image processing algorithms. To try to reconcile the dual requirements of high performance and ease of development, the paper reports on the design and realisation of a high level framework for the implementation of 1D and 2D FFTs for real-time applications. A wide range of FFT algorithms, including radix-2, radix-4, split-radix and fast Hartley transform (FHT) have been implemented under a common framework in order to enable system designers to meet different system requirements. Results show that the parallel implementation of 2D FFT achieves linear speed-up and real-time performance for large matrix sizes. Finally, an FPGA-based parametrisable environment based on 2D FFT is presented as a solution for frequency-domain image filtering application.     

Hybrid Solar Cells Based in Silicon Nanowires: Electronic Simulation and Optimization

Silicon - This paper presents recent progress in computational modeling on blend morphology of silicon nanowires (SiNWs) dispersed in a conjugated polymer poly(3-hexylthiophene) P3HT hybrid solar...     

Genetic algorithm-based initial contour optimization for skin lesion border detection

Multimedia Tools and Applications - Automated segmentation has an essential role in detecting several diseases, such as skin lesions. In segmentation, the active contour (AC) is an efficient method...     

FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration

This paper presents a combination of novel feature vectors construction approach for face recognition using discrete wavelet transform (DWT) and field programmable gate array (FPGA)-based intellectual property (IP) core implementation of transform block in face recognition systems. Initially, four experiments have been conducted including the DWT feature selection and filter choice, features optimisation by coefficient selections and feature threshold. To examine the most suitable method of feature extraction, different wavelet quadrant and scales have been evaluated, and it is followed with an evaluation of different wavelet filter choices and their impact on recognition accuracy. In this study, an approach for face recognition based on coefficient selection for DWT is presented, and the significant of DWT coefficient threshold selection is also analysed. For the hardware implementation, two architectures for two-dimensional (2-D) Haar wavelet transform (HWT) IP core with transpose-based computation and dynamic partial reconfiguration (DPR) have been synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. Experimental results and comparisons between different configurations using partial and non-partial reconfiguration processes and a detailed performance analysis of the area, power consumption and maximum frequency are also discussed in this paper.     

Structural hidden Markov models for biometrics: Fusion of face and fingerprint

The goal of this paper is threefold: (i) propose a novel face and fingerprint feature modeling using the structural hidden Markov models (SHMMs) paradigm, (ii) explore the use of some feature extraction techniques such as ridgelet transform, discrete wavelet transform with various classifiers for biometric identification, and (iii) determine the best method for classifier combination. The experimental results reported in both fingerprint and face recognition reveal that the SHMMs concept is promising since it has outperformed several state-of-the-arts classifiers when combined with the discrete wavelet transform. Besides, this study has shown that the ridgelet transform without principal components analysis (PCA) dimension reduction fits better with the support vector machines (SVMs) classifier than it does with the SHMMs in the fingerprint recognition task. Finally, these results also reveal a small improvement of the bimodal biometric system over unimodal systems; which suggest that a most effective fusion scheme is necessary.     

A GGP approach to solve non convex min-max predictive controller for a class of constrained MIMO systems described by state-space models

This paper proposes a new method to solve non convex min-max predictive controller for a class of constrained linear Multi Input Multi Output (MIMO) systems. A parametric uncertainty state space model is adopted to describe the dynamic behavior of the real process. Moreover, the output deviation method is used to design the j-step ahead output predictor. The control law is obtained by the resolution of a non convex min-max optimization problem under input constraints. The key idea is to transform the initial non convex optimization problem to a convex one by means of variable transformations. To this end, the Generalized Geometric Programming (GGP) which is a global deterministic optimization method is used. An efficient implementation of this approach will lead to an algorithm with a low computational burden. Simulation results performed on Multi Input Multi Output (MIMO) system show successful set point tracking, constraints satisfaction and good non-zero disturbance rejection.     

An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p ²), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations are carried out to analyse the performance of the FRIT core developed.