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无源电容误差平均技术是一种本质线性(Inherently Linear)的流水线模数转换电容失配校准技术,但其转换速度是传统技术的一半.为了提高速度,本文提出了一种改进的电容误差平均技术.该技术从减少一个转换周期所需的时钟相数目和减少每个时钟相的时间两个方面来优化速度.电路分析和MATLAB仿真表明,在两种典型的情况下,改进的技术能将速度提高52%(跨导放大器为开关电容共模反馈)和64%(跨导放大器为非开关电容共模反馈)以上.改进的技术更适用于高速高精度及连续工作的应用场合. 相似文献
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锥形封头广泛用于低压化工容器及设备上。为便于制造,常常选用无折边锥形封头。常规定设计时半锥角α≤30°。但有时出于结构设计和节约钢材的需要,不得不加大半锥角α。文献[1]规定:对于无折边锥形封头,当α>30°时需用应力分析法进行计算。但到目前为止,我国的标准规范还没有正式制定出统一的应力分析计算方法。本文提出了承受内压,半锥角α>30°的无折边锥形封头的应力分析法计算公式,并介绍了电算程序。 相似文献
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A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter(ADC) in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumpt... 相似文献
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采用0.8μm CMOS工艺,实现了一种用于过采样∑-△ A/D转换器的数字抽取滤波器。该滤波器采用多级结构,梳状滤波器作为首级,用最佳一致逼近算法设计的FIR滤波器作为末级,并通过位串行算法硬件实现。芯片测试表明,该滤波器对128倍过采样率、2阶∑-△调制器的输出码流进行处理得到的信噪比为75dB。 相似文献
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提出了一种开关电容流水线结构A/D转换器(ADC)的速度分析方法。流水线结构ADC的速度取决于其级电路中开关电容反馈放大器的建立速度。根据流水线结构的特点,推导出输入等效阶跃电压的计算公式。将建立过程划分为大信号和小信号工作区,分别用不同的跨导运放(OTA)模型进行分析,得出了OTA指标、采样电容值等电路参数与建立时间之间的关系式。通过对一个10 bit流水线结构ADC的MATLAB进行仿真,验证了所提出的分析方法和得到的关系式的有效性。 相似文献
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A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads. 相似文献
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A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW (including I/O drivers) when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads. 相似文献
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This paper presents a 50 Hz 15-bit analog-to-digital converter(ADC) for pixel-level implementation in CMOS image sensors.The ADC is based on charge packets counting and adopts a voltage reset technique to inject charge packets.The core circuit for charge/pulse conversion is specially optimized for low power,low noise and small area.An experimental chip with ten pixel-level ADCs has been fabricated and tested for verification.The measurement result shows a standard deviation of 1.8 LSB for full-scale output.The ADC has an area of 4545 m2 and consumes less than 2 W in a standard 1P-6M 0.18 m CMOS process. 相似文献