Investigation of the action of flame retardants in cellulose. I. Investigation of the flame retardant action of 2,2′-oxybis(5,5-dimethyl-1,3,2-dioxaphosphorinane-2,2′-disulfide) in cellulose

Pyrolysis experiments were performed in high vacuum and under reduced air pressure (100 Pa). The volatile products of pure cellulose and cellulose containing various amounts of flame retardant 2,2′-oxybis (5,5-dimethyl-1,3,2-dioxaphosphorinane-2,2′-disulfide), i.e., Sandoflam 5060 of Sandoz AG, were studied by means of gas chromatography in combination with mass spectroscopy. The volatile products were characterized with infrared spectroscopy. The studied revealed that the incorporation of the flame retardant enhanced the water release and shifted the onset of this reaction to lower temperature. On the basis of these findings an explanation for the mechanism of flame retardancy in generated cellulose fibers modified with this particular flame retardant is attempted. From experiments with different residual air pressure the influence of oxygen on the primary processes of the pyrolytic degradation of cellulose is being discussed.     

Synthesis and characterisation of N-toluyl methacrylatoethyl carbamates,homopolymers and copolymers with methyl methacrylate

The paper describes the synthesis of N-2/4-toluyl methacrylatoethyl carbamates using 2/4-toluyl isocyanate and 2-hydroxyethyl methacrylate. Homopolymerisation and copolymerisation of these novel monomers with methyl methacrylate was carried out using benzoyl peroxide as an initiator and tetrahydrofuran as solvent. Photopolymerisation of N-4-toluyl methacrylatoethyl carbamate could be carried out without the use of photosensitiser. Structural characterisation of copolymers was done using ¹H-NMR. Thermal stability of copolymers was evaluated in a nitrogen atmosphere by dynamic thermogravimetry.     

Network and device-level impacts: performance and reliability of active I/O storage systems

Distributed active storage architectures are designed to offload user-level processing to the peripheral from the host servers. In this paper, we report preliminary investigation on performance and fault recovery designs, as impacted by emerging storage interconnect protocols and state-of-the-art storage devices. Empirical results obtained using validated device-level and interconnect data demonstrate the significance of the said parameters on the overall system performance and reliability.     

Microarchitectures for Managing Chip Revenues under Process Variations

As transistor feature sizes continue to shrink intothe sub-90nm range and beyond, the effects of process variationson critical path delay and chip yields have amplified. A commonconcept to remedy the effects of variation is speed-binning, bywhich chips from a single batch are rated by a discrete range offrequencies and sold at different prices. In this paper, we discussstrategies to modify the number of chips in different bins andhence enhance the profits obtained from them. Particularly, wepropose a scheme that introduces a small Substitute Cacheassociated with each cache way to replicate the data elementsthat will be stored in the high latency lines. Assuming a fixedpricing model, this method increases the revenue by as much as13.8% without any impact on the performance of the chips.