Lifetime optimization of wireless sensor networks with sleep mode energy consumption of sensor nodes

The energy constraint is a major issue in wireless sensor networks since battery cells that supply sensor nodes have a limited amount of energy and are neither replaceable nor rechargeable in most cases. A common assumption in previous work is that the energy consumed by sensors in sleep mode is negligible. With this hypothesis, the usual approach is to iteratively consider subsets of nodes that cover all the targets. These subsets, also called cover sets, are then put in the active mode whereas the others are in the low-power or sleep mode. The scheduling of the appropriate cover sets in order to maximize the network lifetime is a challenging problem known to be NP-hard. The consideration of non-zero energy consumption of sensor nodes in sleep mode is more realistic but significantly increases the complexity of the problem. In this paper, we address this question by proposing a greedy algorithm that gives priority to sensors with lowest energy, and uses a blacklist to limit the number of sensors covering critical targets. Simulations show that this algorithm outperforms the previously published solutions. We then propose for regular arrays, an analytical approach which shows that, for any optimal solution, all sensors’ remaining energies are zero. This theoretical approach sheds a new light on ring connected arrays of odd size, that are known to be rather tricky when non-disjoint cover sets are considered.

     

Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing

The estimation of test metrics such as defect level, test yield or yield loss is important in order to quantify the quality and cost of a test approach. For design-for-test purposes, this is important in order to select the best test measurements but this must be done at the design stage, before production test data is made available. In the analogue domain, previous works have considered the estimation of these metrics for the case of single faults, either catastrophic or parametric. The consideration of single parametric faults is sensitive for a production test technique if the design is robust. However, in the case that production test limits are tight, test escapes resulting from multiple parametric deviations may become important. In addition, aging mechanisms result in field failures that are often caused by multiple parametric deviations. In this paper, we will consider the estimation of analogue test metrics under the presence of multiple parametric deviations (or process deviations) and under the presence of faults. A statistical model of a circuit is used for setting test limits under process deviations as a trade-off between test metrics calculated at the design stage. This model is obtained from a Monte Carlo circuit simulation, assuming Gaussian probability density functions (PDFs) for the parameter and performance deviations. After setting the test limits considering process deviations, the test metrics are calculated under the presence of catastrophic and parametric single faults for different potential test measurements. We will illustrate the technique for the case of a fully differential operational amplifier, proving the validity in the case of this circuit of the Gaussian PDF.

Cramer–Rao lower bounds and maximum likelihood timing synchronization for dirty template UWB communications

Timing acquisition constitutes a major challenge in realizing ultra-wideband communications. In this paper, we propose the timing with dirty template (TDT) approach as a promising candidate for achieving rapid, accurate and low-complexity acquisition. We describe the dirty template (DT) technique, in order to develop and test timing algorithms in both modes: data-aided (DA) and non-data- aided (NDA) modes. First, we derive the Cramer–Rao lower bound, which is used as a fundamental performance limit for any timing estimator. Next, the TDT acquisition estimator is achieved by using the Maximum Likelihood concept. Then we propose a new method, based on Time-Hoping codes, to improve the performance estimation of the original dirty template algorithms. Simulation shows the estimation error results of the modified method in the DA and NDA modes. It confirms the high performance and fast timing acquisition of DA mode, compared with NDA mode, but with less bandwidth efficiency.     

Detection of UWB signal using dirty template approach

This paper handles the problem of detecting ultra-wideband signals in the presence of dense multipath channel and ambient noise. To design a low-complexity high-performance signal detection process, the dirty template approach is proposed. We first explain the dirty template technique and its implementation in UWB communication systems. Then, the Neyman–Pearson theorem is applied to derive the UWB signal detector and select the suitable detection threshold values. Finally, the performance of the proposed dirty template detector is evaluated in terms of the detection and false alarm probabilities for different threshold values, signal-to-noise ratio and number of data-aided symbols.     

Pseudorandom BIST for test and characterization of linear and nonlinear MEMS

In this paper we study the use of the pseudorandom (PR) technique for test and characterization of linear and nonlinear devices, in particular for micro electro mechanical systems (MEMS). The PR test technique leads to a digital built-in-self-test (BIST) technique that is accurate in the presence of parametric variations, noise tolerant, and has high-quality test metrics. We will describe the use of the PR test technique for testing linear and nonlinear MEMS, where impulse response samples of the device under test are considered to verify its functionality. Next, we illustrate and evaluate the application of this technique for linear and nonlinear MEMS characterization.     

On-Chip Pseudorandom MEMS Testing

This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for MEMS. The technique is based on Impulse Response (IR) evaluation using pseudo-random Maximum–Length Sequences (MLS). The MLS approach is capable of providing vastly superior dynamic range in comparison to the straightforward technique using an impulse excitation and is thus an optimal solution for measurements in noisy environments and for low-power test signals. The use of a pseudo-random sequence makes the practical on-chip implementation very efficient in terms of the extra hardware required for on-chip testing. We will demonstrate the use of this technique for an on-chip fast and accurate broadband determination of MEMS behaviour, in particular for the characterisation of cantilever MEMS structures, determining their mechanical and thermal behaviour using just electrical tests.Libor Rufer has received Engineering and PhD degrees from the Czech Technical University, Prague, Czech Republic. Until 1993 he was with the Faculty of Electrical Engineering of the Czech Technical University, Prague and since 1994, he is Associate Professor at the Joseph Fourier University, Grenoble, France. In 1998, he joined the Microsystems research team of the TIMA Laboratory. Currently he is a member of the Reliable Mixed-signal Systems Group of the same Laboratory. His expertise and research interests pertain MEMS-based sensors and actuators, electro-acoustic and electro-mechanical transducers, their modelling, applications, associated measurement techniques, and analogue and mixed-signal system test.Salvador Mir has an Industrial Engineering (Electrical, 1987) degree from the Polytechnic University of Catalonia, Barcelona, Spain, and M.Sc. (1989) and Ph.D. (1993) degrees in Computer Science from the University of Manchester, UK. He is a researcher of Centre National de la Recherche Scientifique, France, and he is leading the RMS (Reliable Mixed-signal Systems) Group at TIMA Laboratory in Grenoble, France. He is the author of many research papers and editor of two books on silicon microsystems. His research interests include analogue, mixed-signal, RF and microsystem design and test, and applications of Artificial Intelligence to Computer-Aided Design.Emmanuel Simeu received Electrical Engineering degree, DEA and Ph.D. in Automatic Control from National Polytechnic Institute of Grenoble in 1987, 1988 and 1992, respectively. He is Associate Professor of Automatic Control and Electrical engineering in Joseph Fourier University of Grenoble. He is also a researcher in the RMS Group at TIMA Laboratory. His research interests include system modelling, reliability of integrated systems, online testing of analogue, digital and mixed signal systems.Christian Domingues was born in Lyon, France, in 1978. He received a Master degree in Microelectronics from the Institut National Polytechnique de Grenoble, France, in 2001. He is currently pursuing a Ph.D. degree at TIMA Laboratory in Grenoble, France. His research interests include mixed-signal integrated circuit design, and micromachined sensors and actuators.     

Novel control for delay-locked loop in IR-UWB communication systems

Timing synchronization represents a major challenge in carrying out highly efficient ultra-wideband (UWB) communications. The delay-locked loop (DLL) method is widely proposed to maintain the satisfactory synchronization and reduce timing error. In this paper, the structure of DLL is modified by using the internal model control (IMC). This novel approach in the telecommunication systems has a good performance of overcoming disturbance and deviations of model parameters. Then the proposed IMC-DLL structure is developed, and by taking a linear Doppler Effect into account. This development is achieved by using the following two approaches: multi-model approach and moving average filter. Finally, the simulation results confirm that the proposed IMC-DLL system is able to achieve satisfactory and accurate tracking even in the presence of Doppler effect, and they also confirm that the proposed DLL has higher transient response, compared with the classical one.     

Design of tracking loop with dirty templates for UWB communication systems

Maintaining satisfactory synchronization between transmitter and receiver is one of the major challenges in carrying out highly efficient ultra-wideband (UWB) communications. For tracking purposes, the delay-locked loop (DLL) concept is applied. The DLL could be considered as a fundamental tracking technique for UWB devices. In this paper, the reference signal is generated at the receiver based on an approach called timing with dirty template. This approach promises to improve tracking performance while reducing receiver structure complexity. After the reference template is generated, we derive first-order and second-order DLL designs for UWB systems. Furthermore, we utilize the benefits of time-hopping codes to enhance noise handling ability of the DLL. Finally, the parameters of the proposed DLL will be selected to optimize tracking behavior in the presence of the ambient noise and Doppler effects. Simulation results show tracking performance across various DLL parameter values.