An easy-to-use mismatch model for the MOS transistor

In this paper, a physics-based mismatch model is presented. It is demonstrated on a 0.18-/spl mu/m technology that a simple mismatch model can still be used to characterize deep-submicron technologies. The accuracy of the model is examined and found to be within 20% in the strong inversion region. Bulk bias dependence is modeled in a physical way. To extract the mismatch parameters, a weighted fit is introduced. It is shown that the width and length dependence of the mismatch parameters is given by the Pelgrom model.     

A large-signal very low-distortion transconductor forhigh-frequency continuous-time filters

A high-frequency large-signal very low-distortion voltage-to-current transducer is presented. The total harmonic distortion (THD), for supply voltages of only ±2.5 V, is smaller than 0.1% for fully differential input signals up to 2.4 V peak to peak (V_pp). The dynamic range is on the order of 89 dB with the transconductor noise integrated over a bandwidth of 1 MHz. Moreover, this structure presents low sensitivity to transistor mismatches. An operational transconductance amplifier (OTA), based on this transconductor, has been used in an adjustable quality factor 1.8-MHz biquadratic continuous-time filter. The quality factor Q is controlled, from 2 to 50, with a novel current-source configuration. Both the OTA and the filter have been fabricated in a CMOS 3-μm n-well process     

A CMOS multiparameter biochemical microsensor with temperaturecontrol and signal interfacing

A fully integrated multiparameter microsensor chip is presented for continuous monitoring of concentrations of different blood gases (e.g., pH, PO₂, pCO₂), ions, and biomolecules, and for conductometric measurements. The chip can monitor up to seven different chemical substances depending on the membranes deposited on the sensor units (on-chip ion-sensitive field-effect transistors (ISFETs), amperometric and conductometric cell). The sensors, which are positioned in a flow channel, are surrounded by on-chip interfacing and processing electronics so that external readout goes via a simple data acquisition card. In addition, temperature control of the measured fluids and a onetime-use security check have been provided for proper operation. Fabrication was done in a standard 1.2-μm CMOS process to which extra postprocessing steps have been added for the chemical sensors and membranes. The chip operates at 5 V and the total die area is 25.7 mm². Full integration is obtained including the ISFETs and ISFET buffers, as well as a reference electrode structure, all integrated on the same chip in the same technology     

A 12-bit intrinsic accuracy high-speed CMOS DAC

A 12-bit intrinsic accuracy digital-to-analog (D/A) converter integrated in a standard digital 0.5 μm CMOS technology is presented. It is based on a current steering doubly segmented 6+2+4 architecture and requires no calibration, no trimming, or dynamic averaging. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 and 0.6 least significant bits (LSB's), respectively. The measured glitch energy is 1.9 pV.s. For a 12-bit resolution, the converter reaches an update rate of 300 MS/s. By reducing the voltage supply of the latches to 2.0 V, the glitch energy is reduced to sub-pV.s, and the update rate reaches 500 MS/s, for a resolution of 8 bits. The worst case power consumption is 320 mW, and it operates from a single 3.3 V voltage supply. The die area is 3.2 mm²     

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chipautomatic tuning

A maximally flat 10.7-MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The signal-to-in-band integrated noise ratio (SNR) of the automatically tuned filter is around 68 dB. The third intermodulation distortion (IM3) is lower than -40 dB for a two-tone input signal of 3.2 V peak to peak (V_p-p). The complete system operates with supply voltages of ±2.5 V. The power consumption of the system is 220 mW. All this has been achieved due to the use of a low-distortion transconductor, the development of a high-frequency CMOS resistor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The chip has been fabricated in a standard 1.5-μm n-well CMOS process     

A Design-Optimized Continuous-Time Delta–Sigma ADC for WLAN Applications

A third-order continuous-time delta-sigma (DeltaSigma) analog-to-digital converter (ADC) is presented for the conversion of an input signal bandwidth of 10 MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed low-power building blocks of the DeltaSigma modulator. From this point of view, it is shown that GmC integrators are preferred over RC integrators in the low-pass filter of the modulator because they show a better tradeoff between power, speed, and accuracy. A new single-bit quantizer topology is presented that incorporates a local feedback path that improves stability using a switched-voltage technique. Finally, a design methodology for the single-bit digital-to-analog converter (DAC) in the feedback loop is proposed, focusing on the impact of high sampling rates on the stability of the converter. The presented continuous-time ADC achieves a simulated dynamic range of 72 dB and a signal-to-noise-and-distortion-ratio of 66 dB in a 10-MHz signal bandwidth. Therefore, it can be applied for WLAN broadband communication. The power consumption of the DeltaSigma modulator is limited to 7.5 mW. The chip is designed in a 0.18-mum triple-well CMOS technology     

A total solution for a 9600-b/s modem transmitter chip

A single-chip analog transmitter (TX chip) for a V29-V32 9600-b/s modem has been implemented in a 3-μm CMOS n-well process. A high level of integration permits a low-cost, high-performance modem to be built. The TX chip is composed of analog, switched capacitor, and digital circuits. The important functions realized are the phase-point generator, the cosine roll-off low-pass filter, the modulator, and the programmable equalization filters. The chip occupies 29 mm² and dissipates 300 mW     

Path-independent integral for the dilatation symmetry group in thermoplasticity

The aim of this study is to establish a fatigue criteria based on an energy threshold corresponding to crack initiation in the case of dilatational symmetry of a structure under thermomechanical loading. An extension of the M integral to thermoplasticity relating to the scaling symmetry is presented. Based on a discrete Lagrangian describing the thermo-inelastic system and Noether's theorem defining the conservation law, the null Lagrangian theorem is applied in order to introduce thermoplasticity. By the use of the divergence theorem, the modified M integral is obtained. Path-domain independence is discussed illustrated by a numerical example.     

A continuous-time delta-sigma modulator for 802.11a/b/g WLAN implemented with a hierarchical bottom-up optimization methodology

This paper presents a 3rd-order continuous-time Delta-Sigma modulator with a resolution of 10 bits for a 10 MHz signal bandwidth. It is designed in a standard 0.18 μm CMOS technology and consumes only 6 mW. After the design/selection of the topologies for the integrators, comparator and D/A converters, optimal sizing of the complete modulator was ensured by using a hierarchical bottom-up, multi-objective evolutionary design methodology. With this methodology, a set of Pareto-optimal modulator designs is generated by using Pareto-optimal performance solutions of the hierarchically decomposed lower-level subblocks. From the generated Pareto-optimal design set, a final optimal design is chosen that complies with the specifications for the 802.11a/b/g WLAN standard and has minimal power consumption.     

Optimal fault detection for analogue circuits under manufacturingtolerances

An optimal method for analogue fault detection is presented. Instead of using arbitrary decision windows, the method fully considers the VLSI manufacturing tolerances and mismatches to minimise the probability of erroneous test decision. A-priori simulated probability information is combined with the actual measurement data to decide whether the circuit is fault-free or faulty. Experimental results show the effectiveness of the proposed technique