Decoding real block codes: activity detection Wiener estimation

New decoding procedures for real-number block codes which are constructed by imposing constraints in the discrete Fourier transform (DFT) domain are examined. The codewords are corrupted by small levels of roundoff noise and possibly occasionally by a few large excursions of random disturbances. The error-correcting procedure is separated into two parts, large activity detection followed by error value estimation, particularly the larger errors. The first part determines if large excursions are present, roughly identifying their locations, while the second part is a Wiener minimum mean-squared error estimation technique providing a stochastic correction to the corrupted components. The activity-detecting part determines locations for large increases in the Wiener estimator's gain. A computationally intensive Bayes hypothesis testing approach is shown to be very effective at locating large activity positions, but a more efficient modified Berlekamp-Massey (1969) algorithm is developed which leads to excellent mean-squared error performance. Extensive simulations demonstrate individual codeword corrective actions and compare the average mean-squared error performance between coded and unprotected data. The error level improvement ranges from three to four orders of magnitude     

Modifying real convolutional codes for protecting digital filteringsystems

A method is presented for protecting the overall realization of digital filters implemented with very dense high-speed electronic devices against both hard and soft errors at the data sample level using the error-detecting properties of real convolutional codes. The normal filter system is surrounded with parallel parity channels defined by a real systematic rate k/n convolutional code. Erroneous behavior is detected by comparing externally the calculated and regenerated parity samples. Significant complexity reductions are possible by modifying the code structure, without loss of error protection, yielding simplified parity channels with finite impulse response (FIR) structures with computational rates decimated by k . The code modification procedure is described. The code modification process has been automated in a computer algorithm. The effects of parity filter quantizations are analyzed and a bound on the mean-square error in the parity comparison is given     

Identification of Specific and Nonspecific Inhibitors of Bacillus anthracis Type III Pantothenate Kinase (PanK)

Antibiotics with novel mechanisms of action are desperately needed to combat the increasing rates of multidrug-resistant infections. Bacterial pantothenate kinase (PanK) has emerged as a target of interest to cut off the biosynthesis of coenzyme A. Herein we report the results of an in vitro high-throughput screen of over 10 000 small molecules against Bacillus anthracis PanK, as well as a follow-up screen of hits against PanK isolated from Pseudomonas aeruginosa and Burkholderia cenocepacia. Nine hits are structurally categorized and analyzed to set the stage for future drug development.     

RNS Digital Filtering Structures for Wafer-Scale Integration

Wafer-scale integration (WSI) compresses a large amount of microelectronics representing a complete digital system onto a single intact wafer. This approach is desirable for applications requiring extensive computational capabilities but only limited input and output connections. Its primary advantage is an improvement in total system density. However, such designs must have built-in fault tolerance. Parallel architectures are ideal for WSI. Thus, digital filtering implemented via the residue number system (RNS) is an application that naturally fits the requirements and advantages of WSI. A finite impulse response (FIR) filter readily lends itself to RNS implementation, and a system architecture employing both RNS and WSI is proposed. Means of introducing inherent fault tolerance using the RNS are briefly covered. After a tutorial introduction to the residue number system, methods of performing addition and multiplication operations in the RNS are explored on the basis of reducing area for a custom VLSI design. Modulo addition implemented with two conventional binary adders provides a compact design that may be externally programmed for the modulus that it operates in. Realization of mod multiplication via index addition is shown to be more effective than implementing the mod multiplication truth table directly. Conversions from binary to the RNS representation and vice versa are major bottlenecks in RNS design. Techniques for conversion into the RNS and out of the RNS based on a sequential division algorithm and the mixed-radix system expansion, respectively, are presented.     

Fault tolerance design in JPEG 2000 image compression system

The JPEG 2000 image compression standard is designed for a broad range of data compression applications. The new standard is based on wavelet technology and layered coding in order to provide a rich feature compressed image stream. The implementations of the JPEG 2000 codec are susceptible to computer-induced soft errors. One situation requiring fault tolerance is remote-sensing satellites, where high energy particles and radiation produce single event upsets corrupting the highly susceptible data compression operations. This paper develops fault tolerance error-detecting capabilities for the major subsystems that constitute a JPEG 2000 standard. The nature of the subsystem dictates the realistic fault model where some parts have numerical error impacts whereas others are properly modeled using bit-level variables. The critical operations of subunits such as discrete wavelet transform (DWT) and quantization are protected against numerical errors. Concurrent error detection techniques are applied to accommodate the data type and numerical operations in each processing unit. On the other hand, the embedded block coding with optimal truncation (EBCOT) system and the bitstream formation unit are protected against soft-error effects using binary decision variables and cyclic redundancy check (CRC) parity values, respectively. The techniques achieve excellent error-detecting capability at only a slight increase in complexity. The design strategies have been tested using Matlab programs and simulation results are presented.     

Systematic Construction of Cyclically Permutable Code Words

A numerical procedure for determining the cyclically permutable code of any length over an arbitrary alphabet is outlined. This method is easily programmed on a digital computer. A formula for the Hamming weight distribution of the code is also given. The results for the 12 bit binary cyclically permutable code are presented along with the weight distribution of the binary codes through length 14.     

Feedback decoding of fixed-point arithmetic convolutional codes

Convolutional codes defined over the integers modulo a power of two, an arithmetic structure used for fixed-point arithmetic computations, employ well-known binary convolutional codes as their underlying generators. A recursive decoding technique that exploits binary expansion components of the code symbols uses any binary decoding algorithm valid for the underlying code.