Study of internal behavior in a vertical DMOS transistor under short high current stress by an interferometric mapping method

Current distribution in vertical double-diffused MOS (DMOS) transistors of a Smart Power Technology are investigated under high current, short duration operation conditions by means of a backside laser interferometric thermal mapping technique. DMOS devices of different areas are studied under pulsed gate forward operation mode and under electrostatic discharge (ESD)-like stress with floating and grounded gate. The internal behavior of the devices observed by thermal mapping under these stress conditions is correlated with the electrical characteristics.     

Thermal distribution during destructive pulses in ESD protection devices using a single-shot two-dimensional interferometric method

Thermal distribution during single destructive electrostatic discharge (ESD) events is investigated in smart power ESD protection devices using a two-dimensional holographic interferometry technique. The hot spot dynamics and the position of destructive current filaments is correlated with the thermal distribution under the nondestructive conditions and with the failure analysis results.     

Moving current filaments in integrated DMOS transistors under short-duration current stress

Integrated vertical DMOS transistors of a 90-V smart power technology are studied under short-duration current pulses. Movement of current filaments and multiple hot spots observed by transient interferometric mapping under nondestructive snap-back conditions are reported. Device simulations show that the base push-out region associated with the filament can move from cell to cell along the drain buried layer due to the decrease of the avalanche generation rates by increasing temperature. The influence of the termination layout of the source field on the hot-spot dynamics is studied. Conditions for filament motion are discussed. The described mechanisms help homogenizing the time averaged current-density distribution and enhance the device robustness against electrostatic discharges.     

Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology

Substrate current distribution as trigger for external latch-up (LU) and transient latch-up (TLU) is analyzed by optical transient interferometric mapping (TIM) technique. The transient free carrier (plasma) concentration related to substrate current flow is studied for various guard-ring configurations and injection carrier type on special test structures and real I/O cells. TIM uncovers proximity effects in I/O cells causing substrate current crowding which are important for the definition of effective LU protection concepts.     

Explanation of threshold voltage scaling in enhancement-mode InAlN/AlN-GaN metal oxide semiconductor high electron mobility transistors on Si substrates

We present enhancement-mode GaN high electron mobility transistors on Si substrates with ZrO₂ gate dielectrics of thicknesses t_ox between 10 and 24 nm. The oxide interlayers between the InAlN/AlN barrier and gate metal allow raising the device threshold voltage up to + 2.3 V and reduce gate leakage current to less than 100 nA/mm with a high drain current on/off ratio of 4 orders of magnitude. We use a model that explains the observed linear dependence of the threshold voltage on t_ox and allows determining fixed charges at the oxide/barrier interface.     

Application of transient interferometric mapping method for ESD and latch-up analysis

Transient Interferometric Mapping (TIM) tools are reviewed from a perspective of their particular application area and comparison to other transient optical analysis techniques. TIM studies on trigger behavior, current filamentation and failure modes in BCD DMOS and ESD protection devices under TLP and system-level-ESD – like pulses are overviewed. TIM analysis of CMOS ESD protection devices, in particular study of on-state spreading effect in 90 nm SCRs is also presented. Furthermore TIM investigations of substrate currents and parasitic SCR paths during transient latch-up events in 90 nm CMOS and BCD technology test structures and products are reviewed. Finally TIM studies of ESD and short-time self-heating phenomena in GaN HEMTs and lasers are also briefly mentioned.     

Bulk and surface degradation mode in 0.35μm technology gg-nMOS ESD protection devices

We study failure mechanisms in 0.35μm process grounded-gate nMOS electrostatic discharge (ESD) protection devices stressed by high current - ESD like - pulses. Stress evolution of leakage current and low frequency noise is correlated with the position of the ESD damage analyzed using optical beam induced current (OB1C) technique. While a kink-free-like IV characteristics and low noise magnitude are typical for a bulk damage at the drain-contact region, a kink-like IV shape and large random telegraph signal (RTS) noise accompanies surface damage under the gate oxide. The role of hot-carriers in the degradation of the Si/Si0₂ interface and gate oxide, and leakage current mechanism are discussed.     

Thermal and free carrier concentration mapping during ESD event in smart Power ESD protection devices using an improved laser interferometric technique

Spatial distribution of temperature and free-carrier concentration during high-current stress is studied in smart power electrostatic discharge (ESD) protection devices using a backside laser interferometric technique. The method is based on detecting changes in the refractive index of silicon due to thermo-optical and plasma-optical effects. We use a modified version of a heterodyne interferometer, where the reference beam is reflected from an external mirror outside the sample chip, which allows one to perform measurements without any restriction to the size of the scanning area. We have found two pronounced heat dissipating regions due to a vertical and a lateral current flow path in the device. In addition, two regions with increased current density due to carrier injection related to the two current paths have been found. These temperature and carrier concentration distributions found by the experiment agree very well with the results of 2D device simulation.     

Quantitative X-ray projection microscopy: phase-contrast and multi-spectral imaging

We outline a new approach to X‐ray projection microscopy in a scanning electron microscope (SEM), which exploits phase contrast to boost the quality and information content of images. These developments have been made possible by the combination of a high‐brightness field‐emission gun (FEG)‐based SEM, direct detection CCD technology and new phase retrieval algorithms. Using this approach we have been able to obtain spatial resolution of < 0.2 µm and have demonstrated novel features such as: (i) phase‐contrast enhanced visibility of high spatial frequency image features (e.g. edges and boundaries) over a wide energy range; (ii) energy‐resolved imaging to simultaneously produce multiple quasi‐monochromatic images using broad‐band polychromatic illumination; (iii) easy implementation of microtomography; (iv) rapid and robust phase/amplitude‐retrieval algorithms to enable new real‐time and quantitative modes of microscopic imaging. These algorithms can also be applied successfully to recover object–plane information from intermediate‐field images, unlocking the potentially greater contrast and resolution of the intermediate‐field regime. Widespread applications are envisaged for fields such as materials science, biological and biomedical research and microelectronics device inspection. Some illustrative examples are presented. The quantitative methods described here are also very relevant to projection microscopy using other sources of radiation, such as visible light and electrons.