On the Mechanisms Governing Aluminum-Mediated Solid-Phase Epitaxy of Silicon

Mechanisms governing the aluminum-mediated solid-phase epitaxy of Si on patterned crystalline Si substrates have been identified by studying the deposited material as a function of growth conditions when varying parameters such as temperature, growth time, and layer-stack properties. Early growth stages can be discerned as first formation of “free” Si at the Al/α-Si interface, then diffusion of Si along the Al grain boundaries, nucleation at the Si substrate surface, nuclei rearrangement, and finally crystal growth. The acquired understanding is applied to control the selectivity and completeness of single-crystal growth in various sizes of contact windows to the Si substrate.     

Aluminum nitride for heatspreading in RF IC’s

To reduce the electrothermal instabilities in silicon-on-glass high-frequency bipolar devices, the integration of thin-film aluminum nitride as a heatspreader is studied. The AlN is deposited by reactive sputtering and this material is shown to fulfill all the requirements for actively draining heat from RF IC’s, i.e., it has good process compatibility, sufficiently high thermal conductivity and good electrical isolation also at high frequencies. The residual stress and the piezoelectric character of the material, both of which can be detrimental for the present application, are minimized by a suitable choice of deposition conditions including variable biasing of the substrate in a multistep deposition cycle. Films of AlN as thick as 4 μm are successfully integrated in RF silicon-on-glass bipolar junction transistors that display a reduction of more than 70% in the value of the thermal resistance.     

Bipolar integrated Kelvin test structure for contact resistancemeasurement of self-aligned implantations

A Kelvin contact resistance test structure has been developed for accurate measurement of highly-doped, shallow n⁺ and p⁺ implantations, which are self-aligned to the contact window. Here the structure has been integrated, without additional processing, in a 30 GHz washed-emitter-base n-p-n bipolar process, for the purpose of monitoring the emitter contact resistance. Diffusion taps to the emitter have been made with the phosphorus collector-plug implantation. Phosphorus evaporation from the contact window during the anneal step and the low sheet resistance of the collector-plug implantation, together with the overall design of the test structure, assure a very accurate determination of the emitter contact resistance even in situations where complete junction isolation of the diffusion taps is not directly possible. Results are presented for the optimization of the emitter anneal cycle with respect to the emitter contact resistance     

Electrothermal characterization of silicon-on-glass VDMOSFETs

Electrothermal consequences of implementing bulk-silicon RF power MOS processes in the silicon-on-glass substrate transfer technology are investigated in this paper. Fabricated silicon-on-glass vertical double-diffused MOSFETs are measured on-wafer and very large thermal resistance values are extracted for each design. The influence of the thermal resistance on RF performance is analyzed, and it is shown that strong electrothermal feedback severely lowers the power capability and strongly increases the operating temperature. A combination of low-thermal contacting and surface mounting to thermally conducting printed circuit board is shown to be very efficient in reducing the large thermal resistance. Numerical thermal simulations demonstrate that surface-mounted silicon-on-glass transistors can have lower thermal resistance than the bulk-silicon device with a wafer thickness reduced down to 100 μm.     

Sub-500/spl deg/C solid-phase epitaxy of ultra-abrupt p/sup +/-silicon elevated contacts and diodes

A well-controlled low-temperature process, demonstrated from 350/spl deg/C to 500/spl deg/C, has been developed for epitaxially growing elevated contacts and near-ideal diode junctions of Al-doped Si in contact windows to the Si substrate. A physical-vapor-deposited (PVD) amorphous silicon layer is converted to monocrystalline silicon selectively in the contact windows by using a PVD aluminum layer as a transport medium. This is a solid-phase-epitaxy (SPE) process by which the grown Si is Al-doped to at least 10/sup 18/ cm/sup -3/. Contact resistivity below 10/sup -7/ /spl Omega//spl middot/cm/sup 2/ is achieved to both p/sup -/ and p/sup +/ bulk-silicon regions. The elevated contacts have also been employed to fabricate p/sup +/-n diodes and p/sup +/-n-p bipolar transistors, the electrical characterization of which indicates a practically defect-free epitaxy at the interface.     

Surface-passivated high-resistivity silicon substrates for RFICs

Surface passivation of high-resistivity silicon (HRS) by amorphous silicon thin-film deposition is demonstrated as a novel technique for establishing HRS as a microwave substrate. Metal-oxide-silicon (MOS) capacitor measurements are used to characterize the silicon surface properties. An increase of the quality factor (Q) of a 10-nH spiral inductor by 40% to Q=15 and a 6.5-dB lower attenuation of a coplanar waveguide (CPW) at 17 GHz indicate the beneficial effect of the surface passivation for radio frequency (RF) and microwave applications. Regarding CPW attenuation, a nonpassivated 3000-/spl Omega//spl middot/cm substrate is equivalent to a 70-/spl Omega//spl middot/cm passivated substrate. Surface-passivated HRS, having minimum losses, a high permittivity, and a high thermal conductivity, qualifies as a close-to-ideal radio frequency and microwave substrate.     

用阶梯状掺杂埋层对超浅结进行C-V剖面分析

研究了应用双边C-V法测量超浅结(如p+-n结)的掺杂分布。推导了在已知p+-n结的电容-电压(C-VR)关系、n区掺杂、以及热平衡下n区耗尽层宽度(xn0)的情况下计算p区掺杂浓度分布的公式。xn0是计算p区掺杂分布所需的一个关键参数,通过将n区掺杂设计成阶梯状,可实现对xn0的精确提取。用Medici对具有相同的阶梯状掺杂n区的p+-n和n-肖特基结进行器件仿真可得其C-VR关系。运用常规C-V法,由肖特基结的C-VR关系可提取出n区掺杂浓度。实现了对xn0的精确提取,其精度达1.8nm。基于精确的xn0,运用双边C-V法提取的p+区的掺杂浓度分布与Medici仿真结果非常吻合。     

Arsenic-spike epilayer technology applied to bipolar transistors

For the first time, epilayers with an arsenic-doped spike of 50 nm width have been grown and used in silicon bipolar junction transistors (BJTs). The epilayer has been optimized such that the collector-base junction of the BJT is formed within the arsenic spike. The counterdoping of boron out-diffusion by arsenic strongly reduces the basewidth. The portion of the spike that is not counterdoped increases the total amount of n-type doping in the collector without reducing BV _ceo. The increased collector-doping allows a 60% higher collector current prior to f_T fall-off. Arsenic has a low diffusivity so very few constraints are put on the thermal budget of the final process. This high flexibility makes the presented epilayer technology a promising candidate to enhance a bipolar process significantly     

Low-stress nitride as oxidation mask for submicrometre LOCOSisolation

A large reduction in the LOCOS bird's beak is obtained by using a thick silicon nitride layer as an oxidation mask. Stress induced damage of the devices is avoided by using low-stress silicon-rich nitride