A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIWgeometry processor with SIMD instructions and a software bypassmechanism

A four-way very long instruction word (VLIW), 312-MHz geometry processor with peripheral component interconnect/accelerated graphic port bus bridge was implemented in a 0.21-μm, 2.5-V, three-layer-metal CMOS process. We adopted (1) a software bypass mechanism, (2) single-instruction multiple-data stream instructions, (3) four sets of floating-point multiply add and accumulate execution units, (4) special condition code registers and a branch condition generator for a clipping operation, and (5) automatic clock delay tuning methodology. As a result of these features, we achieved a performance of 2.5 GFLOPS and 6.5 million polygons per second for a three-dimensional geometry processor, which is the highest published performance as a single geometry processor. The processor is applicable to computer-aided-design systems that require very high graphics performance     

Fluorescent in situ hybridization in combination with filter cultivation (FISHFC) method for specific detection and enumeration of viable Clostridium perfringens

To reduce time for enumeration of viable Clostridium perfringens, fluorescence in situ hybridization in combination with filter cultivation (FISHFC) was employed. The method utilized a CLP-180 probe, based on the 16S rRNA region of C. perfringens, and FISHFC fluorescence microscopy to detect C. perfringens, but not organisms from other species. Optimal cultivation requirements for micro-colony formation were TSC medium, anaerobic conditions, 37 °C, and incubation for 6 h. Under these conditions, micro-colony diameters reached 100 μm, a size sufficient for hybridization. Enumeration of C. perfringens using the CLP-180-aided FISHFC method was realized in 9 h as compared to 3–5 days required by the conventional plate count method. Moreover, viable C. perfringens counts of food samples from the two methods were not significantly different.     

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessorfor multimedia applications

We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and graphic processing capabilities for three-dimensional images, (b) programming flexibility, and (c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set. This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84×10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V