High dynamic range InP HBT delta-sigma analog-to-digital converters

To date, the development of multifunction multicarrier digital receivers for cellular base station and military communications applications has been limited by the demanding dynamic range requirements for the analog-to-digital converter (ADC). The use of oversampling delta-sigma modulators provides a promising approach to overcoming the dynamic range barriers Nyquist-rate converters face in the same applications. This paper discusses issues involved in the design of high-speed high dynamic range wide-band delta-sigma ADCs for such communications applications. Test results of prototype designs are also presented. The delta-sigma modulators described in this paper operate at sampling frequencies ranging from 1 to 2.5 GHz with center frequencies ranging from dc to 100 MHz, providing between 74 and 84.2 dB signal-to-noise ratio (12 and 13.7 bits) for bandwidths of 25 and 12.5 MHz, respectively. The loop filters are continuous-time low-pass and bandpass implementations of order 6 and 10, and were fabricated in an InP heterojunction bipolar (HBT) technology. A typical tenth-order design consumes 6 W of power and occupies a die area of 23.5 mm/sup 2/.     

A sigma-delta-based sparse synthetic aperture beamformer for real-time 3-D ultrasound

Sigma-delta (ΣΔ) modulation allows delay resolution in ultrasound beamformers to be achieved by simple clock cycle delays applied to the undecimated bitstream, greatly reducing the complexity of the signal processing and the number of bits in the datapath. The simplifications offered by this technique have the potential for low power and portable operation in advanced systems such as 3-D and color Doppler imagers. In this paper, an architecture for a portable, real-time, 3-D sparse synthetic aperture ultrasound beamformer based on ΣΔ modulation is presented, and its simulated performance is analyzed. Specifically, with a 65-element linear phased array and three transmit events, this architecture is shown to achieve a 1.1° beamwidth, a -54-dB secondary lobe level, and a theoretical frame rate of 1700 frames/s at λ/64 delay resolution using a second-order low pass ΣΔ modulator. Finally, a technique for modifying the proposed multi-beam architecture to allow improved analog-to-digital (A/D) resolution by premodulating the input signal for bandpass ΣΔ modulation is also presented     

A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture

A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is yet scalable to high sampling rates is presented. To eliminate timing skews, a Nyquist rate sampling switch is used, which is followed by subsampled, double-sampled time-interleaved sample-and-hold (S/H) stages. This circuit is configured with a special clocking scheme that reduces the loading of the interleaved S/Hs on the Nyquist rate sampling switch, making this scalable to high sampling rates. The subsampled ADCs (sub-ADCs) in this design use a 3.5-bit/stage pipelined architecture. This 1-GS/s 11-bit ADC achieves 55-dB peak SNDR, 58.6-dB SNR, consumes 250-mW core power, and occupies a core area of 3.5 mm². This circuit is implemented in a dual-gate 1.2 V/2.5 V, 0.13-mum logic CMOS process     

A SPICE model for a novel brushless adjustable-speed drive

A SPICE circuit model was developed to accurately simulate the i-v characteristics of a brushless AC motor commutated by semiconductor switches. The model is based on Fourier curve fits to measured mutual inductance interactions between all combinations of field and armature windings, as well as coil resistance and inductance. The model is able to accurately predict current and voltage characteristics, both statically, and dynamically when interfaced with a commutation model. The model has been demonstrated to agree with electrical tests of an inverted motor on a large time scale. It has also given reliable predictions of small time-scale details, where it is desirable to predict power MOSFET switch behavior after a command to open or close. Data were collected and analyzed for simulations of the motor model combined with a commutation model containing MOSFET switches. Metrics were compared to data collected from an inverted brushless motor with good agreement.