A negative Vth cell architecture for highly scalable,excellently noise-immune, and highly reliable NAND flash memories

A new, negative V_th cell architecture is proposed where both the erased and the programmed state have negative V_th. This architecture realizes highly scalable, excellently noise-immune, and highly reliable NAND flash memories. The program disturbance that limits the scaling of a local oxidation of silicon (LOCOS) width in a conventional NAND-type cell is drastically reduced. As a result, the scaling limit of the LOCOS width decreases from 0.56 to 0.45 μm, which leads to 20% isolation width reduction. The proposed cell is essential for the future scaled shallow trench isolated cells because improved program disturb characteristics can be obtained irrespective of the process technology or feature size. New circuit techniques, such as a PMOS drive column latch and a V_cc-bit-line shield sensing method are also utilized to realize the proposed cell operation. By using these novel circuit technologies, array noise, such as a source-line noise and an inter bit line capacitive coupling noise, are eliminated. Consequently, the V_th fluctuation due to array noise is reduced from 0.7 to 0.1 V, and the V_th distribution width decreases from 1.2 to 0.6 V. In addition to the smaller cell size and the high noise immunity, the proposed cell improves device reliability. The read disturb time increases by more than three orders of magnitude, and a highly reliable operation can be realized     

A 16-ns 1-Mb CMOS EPROM

A 16-ns 1-Mb CMOS EPROM has been developed utilizing high-speed circuit technology and a double-metal process. In order to achieve the fast access time, a differential sensing scheme with address transition detection (ATD) is used. A double-word-line structure is used to reduce word-line delay. High noise immunity is obtained by a bit-line bias circuit and data-latch circuit. Sufficient threshold voltage shift (indispensable for fast access time) is guaranteed by a threshold monitoring program (TMP) scheme. The array is organized as 64 K×16 b, which is suitable for 32-b high-performance microprocessors. The active power is 425 mW, the programming time is 100 μs, and the chip size is 4.94×15.64 mm²     

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique

To meet the increasing demand for higher-density and faster EPROMs, a 16-Mb CMOS EPROM has been developed based on 0.6-μm N-well CMOS technology. In scaled EPROMs, it is important to guarantee device reliability under high-voltage operation during programming. By employing internal programming-voltage reduction and new stress relaxation circuits, it is possible to keep an external programming voltage V_pp of 12.5 V. The device achieves a 62-ns access time with a 12-mA operating current. A sense-line equalization and data-out latching scheme, made possible by address transition detection (ATD), and a bit-line bias circuit with two types of depletion load led to the fast access time with high noise immunity. This 16-Mb EPROM has pin compatibility with a standard 16-Mb mask-programmable ROM (MROM) and is operative in either word-wide or byte-wide READ mode. Cell size and chip size are 2.2 μm×1.75 μm and 7.18 mm×17.39 mm, respectively     

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM

A 32 Mb NAND type flash EEPROM has been developed with 0.425 μm CMOS technology. A 35 ns cycle time is achieved by adopting a pipeline scheme. A boosted word-line scheme and a program verify operation achieving tight threshold voltage (Vth) distribution of programmed cells reduce read-out access time. Multiple block erase operation is realized by adopting erase block registers. All functions are operable with a single 5.3 V or 5 V power supply     

Design methodology of a robust ESD protection circuit for STIprocess 256 Mb NAND flash memory

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n^- junction with n⁺ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness     

A 130-mm2, 256-Mbit NAND flash with shallow trenchisolation technology

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm², which realizes a 130-mm² , 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput     

A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed

A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13-/spl mu/m CMOS STI technology. The effective cell size including the select transistors is 0.077 /spl mu/m/sup 2/. To decrease the chip size, a new architecture is introduced. The in-series connected memory cells are increased from 16 to 32. Furthermore, as many as 16 k memory cells are connected to the same wordline. As a result, the chip size is decreased by 15%. A very small die size of 125 mm/sup 2/ and an excellent cell area efficiency of 70% are achieved. As for the performance, a very fast programming and serial read are realized. The highest program throughput ever of 10.6-MByte/s is realized: 1) by quadrupling the page size and 2) by newly introducing a write cache. In addition, the garbage collection is accelerated to 9.4-MByte/s. In addition, the write cache accelerates the serial read operation and a very fast 20-MByte/s read throughput is realized.     

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.     

A source-line programming scheme for low-voltage operation NANDflash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme