Single event soft error in advanced integrated circuit

As technology feature sizes decrease, single event upset (SEU), and single event transient (SET) dominate the radiation response of microcircuits. Multiple bit upset (MBU) (or multi cell upset) effects, digital single event transient (DSET) and analogue single event transient (ASET) caused serious problems for advanced integrated circuits (ICs) applied in a radiation environment and have become a pressing issue. To face this challenge, a lot of work has been put into the single event soft error mechanism and mitigation schemes. This paper presents a review of SEU and SET, including: a brief historical overview, which summarizes the historical development of the SEU and SET study since their first observation in the 1970's; effects prominent in advanced technology, which reviews the effects such as MBU, MSET as well as SET broadening and quenching with the influence of temperature, device structure etc.; the present understanding of single event soft error mechanisms, which review the basic mechanism of single event generation including various component of charge collection; and a discussion of various SEU and SET mitigation schemes divided as circuit hardening and layout hardening that could help the designer meet his goals.     

A four-interleaving HBD SRAM cell based on dual DICE for multiple node collection mitigation

A 4-interleaving cell of 2-dual interlocked cells (DICE) is proposed, which reduces single event induced multiple node collection between the sensitive nodes of sensitive pairs in a DICE storage cell in 65 nm technology. The technique involves the 4-interleaving of dual DICE cells at a layout level to meet the required spacing between sensitive nodes in an area-efficient manner. Radiation experiments using a 65 nm CMOS test chip demonstrate that the LETth of our 4-interleaving cell of dual DICE encounters are almost 4× larger and the SEU cross section per bit for our proposed dual DICE design is almost two orders of magnitude less compared to the reference traditional DICE cell.     

一种低功耗抗辐照加固256kb SRAM的设计

设计了一个低功耗抗辐照加固的256kbSRAM。为实现抗辐照加固，采用了双向互锁存储单元（DICE）构以及抗辐照加固版图技术。提出了一种新型的灵敏放大器，采用了一种改进的采用虚拟单元的自定时逻辑来实现低功耗。与采用常规控制电路的SRAM相比，读功耗为原来的11％，读取时间加快19％。     

一种抗单粒子多节点翻转的存储单元

为解决纳米CMOS工艺下单粒子多节点翻转的问题,提出了一种加固存储单元(RH-12T)。在Quatro-10T存储单元基础上对电路结构进行改进,使存“0”节点不受高能粒子入射的影响,敏感节点对的数目是晶体管双立互锁(DICE)存储单元的一半。基于敏感节点对分离和SET缩减原理,进行了加固存储单元版图设计。在相同设计方法下,该存储单元的敏感节点间距是DICE存储单元的3倍。抗SEU仿真结果表明,该存储单元具备单节点翻转全加固能力。全物理模型单粒子瞬态仿真结果表明,该存储单元的线性能量转移 (LET)翻转阈值为DICE存储单元的2.8倍,能有效缓解单粒子多节点翻转的问题。