一种应用于无线局域网收发机的0.13 μm CMOS ΔΣ 分数型频率综合器

本文提出一种应用于IEEE 802.11b/g 无线局域网收发机的ΔΣ 分数型频率综合器。该设计采用了0.13 μm CMOS 工艺。LC型的压控振荡器采用了片上集成的差分电感。分数分频器由吞脉冲式分频器和带噪声整形技术的3阶MASH类型的ΔΣ调制器构成。测试结果表明,参考频率为20 MHz环路带宽为100 kHz的情况下,该设计所有信道的相位噪声性能均可达到带内-93 dBc/Hz,带外-118 dBc/Hz。积分均方相位误差小于0.8。整个设计在1.2V电源条件下消耗8.4 mW的功耗,占用0.86 mm2的面积。     

A 0.13μm CMOS Δ ∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network(WLAN) transceivers.A monolithic LC voltage controlled oscillator(VCO) is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping(MASH)△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm~2.     

一种应用于IEEE 802.11 b/g/n无线局域网收发机的CMOS模拟基带电路

本文提出了一种应用于直接变频无线局域网收发机的模拟基带电路,该电路采用标准的0.13微米CMOS工艺实现,包括了采用有源RC方式实现的接收4阶椭圆低通滤波器、发射3阶切比雪夫低通滤波器、包含直流失调消除伺服环路的接收可变增益放大器及片上输出缓冲器。芯片面积共1.26平方毫米。接收基带链路增益可在-11dB至49dB间以2dB步长调节。相应地,基带接收输入等效噪声电压（IRN）在50 nV/sqrt(Hz) 至30.2 nV/ sqrt(Hz)间变化而带内输入三阶交调（IIP3）在21dBm至-41dBm间变化。接收及发射低通滤波器的转折频率可在5MHz、10MHz及20MHz之间选择以符合包含802.11b/g/n的多种标准的要求。接收基带I、Q两路的增益可在-1.6dB至0.9dB之间以0.1dB的步长分别调节以实现发射IQ增益失调校正。通过采用基于相同积分器的椭圆滤波器综合技术及作用于电容阵列的全局补偿技术,接收滤波器的功耗显著降低。工作于1.2V电源电压时,整个芯片的基带接收及发射链路分别消耗26.8mA及8mA电流。     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier (VGA) with novel DC offset calibration loop for direct-conversion receiver (DCR) is proposed in this paper. The proposed VGA uses the differential-ramp based technique, digitally programmable gain amplifier (PGA) can be converted to analog controlled dB-linear VGA. An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design. The proposed VGA shows a 57dB linear range. The DC offset cancellation (DCOC) loop is based on a continuous time feedback that includes Miller effect and linear rang operation MOS transistor to realize large value capacitor and resistor to solve the DC offset problem, respectively. The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement. Fabricated in SMIC 0.13 m CMOS technology, this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58mm2 of chip area including bondpads. In addition, the DCOC circuit shows 500Hz high pass cutoff frequency (HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

A 55 nm CMOS △∑fractional-N frequency synthesizer for WLAN transceivers with low noise filters

A fully integrated ΔΣ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network(WLAN) transceivers.A low noise filter,occupying a small die area,whose power supply is given by a high PSRR and low noise LDO regulator,is integrated on chip.The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm2 excluding PAD.Measurement results show that in all channels,the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz.The integrated RMS phase error is no more than 0.6°.The proposed synthesizer consumes a total power of 15.6 mW.     

A △∑ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique

A △∑ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise （from 10 to 100 kHz） below -108 dBc/Hz and out-of-band phase noise of -122.9 dBc/Hz （at 1 MHz offset） are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.     

一种适用于双模（GPS与Compass）卫星导航定位接收机的全集成频率综合器设计

本文提出一种适用于双模（GPS与Compass）卫星导航定位接收机的0.13 μm CMOS全集成频率综合器。该设计采用了片上集成的差分电感和片上集成的环路滤波器。为节省芯片面积,环路滤波器的片上集成设计运用了电容倍增技术。分频器设计采用带Mash型ΔΣ调制器的吞脉冲计数器式结构。参考频率为16.368 MHz时,该频率综合器可分别工作在整数或分数模式下,产生频率为1571.328 MHz和1568.259 MHz的本振信号。测试结果表明,该频率综合器的闭环相位噪声性能在100 kHz和1 MHz频偏处可分别达到-91.3 dBc/Hz及-117 dBc/Hz。整个设计在1.2V电源条件下消耗8.6 mA的电流,占用0.92 mm2的面积。     

一种应用于调频接收机，使用低噪声滤波器和量化噪声抑制技术的ΔΣ分数型频率综合器

本文提出一种应用于调频接收机的ΔΣ 分数型频率综合器,该设计采用130nm CMOS 工艺流片。该设计集成了一种占据较小芯片面积,并可以有效降低输出噪声的低噪声滤波器。同时,采用了通过减小分频器步长所实现的量化噪声抑制技术。该频率合成器不需要使用片外元器件,占用0.7 mm2的面积。测试结果表明,环路带宽为200 kHz的情况下,从10 kHz到100 kHz频偏处的带内相位噪声低于-108 dBc/Hz,1 MHz频偏处的带外相位噪声达到-122.9 dBc/Hz。量化噪声抑制技术使带内和带外相位噪声分别降低15dB和7dB。积分均方相位误差小于0.48°。整个频率综合器消耗7.4mW的功耗,频率精度小于1 Hz。