低功耗电流模互连电路的快速优化设计方法

为对低功耗电流模互连电路进行快速优化,提出了一种"自顶向下"的动态驱动电流模互连电路的快速优化设计方法.方法首先对动态驱动电流模电路进行行为级建模,并采用MATLAB对数据进行处理优化电路功耗,确定出最优的电流源电流大小.然后利用"2ID/gm"方法,快速而准确地确定出相应MOS管尺寸.同时,也对"2ID/gm"的模拟集成电路设计方法,进行了较为详细的理论分析.仿真结果表明:使用该方法确定出的MOS管尺寸得到的性能十分接近设计指标,只需通过少量修改便可完成设计.该方法大大提高了设计效率.     

Process variation robust current-mode on-chip interconnect signaling scheme

We propose a novel bias circuit, which can help a promising current-mode signaling （CMS） scheme （CMS-bias） enhance the robustness against process variation but consume less energy than the original bias circuit in this scheme. Monte Carlo and process corner analysis are carried out using HSPICE in the Global Foundry 0.18 μm process. Monte Carlo analysis shows that the CMS-bias with proposed bias circuit （CMS-proposed） and the CMS-bias with original circuit （CMS-original） have the same robustness against the variation, but the former offer a 9% reduction in power consumption. The process corner analysis shows that the average power and delay of the CMS-proposed don＇t change much in different process corners, especially in FS and SF corner. In addition, parameter sensitivity analysis shows that the process variation in long wires has little influence on the delay of the CMS scheme, but the variation in the effective length of MOSFETs influences the performance of the CMS scheme very much.