Challenges towards large-scale fuel cell production: Results of an expert assessment study

Fuel cell electric vehicles are a promising alternative on the way to emission-free mobility. However, there is still a great deal of uncertainty as to how this change can be implemented technologically. Despite various research and development activities on fuel cells in the past two decades, a real breakthrough of fuel cell technology has not yet been reached. The aim of this paper is therefore to identify barriers to a commercialized production of PEM fuel cell stacks. For this purpose, a comprehensive expert study is performed, consisting of a qualitative, exploratory and a quantitative, hypothesis-confirming step. As a result, technical and non-technical barriers are examined and described in this paper. A cost estimation of today's actual manufacturing cost is presented as identified in the study. Conclusively, future research topics and needs for action are derived.     

Overcoming data locality: An in-memory runtime file system with symmetrical data distribution

In many-task computing (MTC), applications such as scientific workflows or parameter sweeps communicate via intermediate files; application performance strongly depends on the file system in use. The state of the art uses runtime systems providing in-memory file storage that is designed for data locality: files are placed on those nodes that write or read them. With data locality, however, task distribution conflicts with data distribution, leading to application slowdown, and worse, to prohibitive storage imbalance. To overcome these limitations, we present MemFS, a fully symmetrical, in-memory runtime file system that stripes files across all compute nodes, based on a distributed hash function. Our cluster experiments with Montage and BLAST workflows, using up to 512 cores, show that MemFS has both better performance and better scalability than the state-of-the-art, locality-based file system, AMFS. Furthermore, our evaluation on a public commercial cloud validates our cluster results. On this platform MemFS shows excellent scalability up to 1024 cores and is able to saturate the 10G Ethernet bandwidth when running BLAST and Montage.     

Scalable control plane for intra-domain communication in software defined information centric networking

Recently there has been a new emerging trend in integrating Information Centric Networking (ICN) and Software Defined Networking (SDN) together in the future Internet research area. Software defined information centric networking (SD-ICN) may face more serious scalability problem in control plane compared with traditional SDN environment due to new features about in-network caching and content-based communication. In this paper, we propose a scalable area-based hierarchical architecture (SAHA) for intra-domain communication to address the control plane scalability problem in SD-ICN. The SAHA supports scalable awareness of network resources and content resources, as well as guarantees efficient interest matching and resource adaptation. Simulation experiments under OMNET++ show that the proposed SAHA can achieve outstanding scalability in resource awareness and content-based communication.     

Design-for-testability techniques for CORDIC design

In this paper, we propose two C-testable design-for-testability (DFT) architectures for coordinate rotation digital computer (CORDIC) design. The first design is achieved by using scalable cells. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between hardware overhead (HO) and number of test patterns (NTP). Both HO and NTP change as n varies. By adjusting the value of n, we can obtain an optimal balance between HO and NTP. Based on these scalable cells, the iterative logic array (ILA) will be still C-testable. For the first proposed design, the HO and NTP for n=2 are 5.37% and 74, respectively. The second one is achieved by the reorganized test sequences, where the HO and NTP are only 3.15% and 18, respectively. The first design can be connected into a non-homogenous ILA for saving lot of test pins and built-in self-test (BIST) area; in the second one, the special properties of the sequences reduce HO/NTP significantly.     

ScalaTrace: Scalable compression and replay of communication traces for high-performance computing

Characterizing the communication behavior of large-scale applications is a difficult and costly task due to code/system complexity and long execution times. While many tools to study this behavior have been developed, these approaches either aggregate information in a lossy way through high-level statistics or produce huge trace files that are hard to handle.     

Scalable reconfigurable equipment design principles

Scalability is one of six key characteristics found in reconfigurable manufacturing systems. Scalable systems satisfy changing capacity requirements efficiently through system reconfiguration, and in the flexible manufacturing literature this capability is called expansion flexibility. The development of modular scalable machine tools is a necessary precursor to achieving scalable systems. Unfortunately, there is little work describing the design of scalable machines. This paper establishes the need for scalable machines and a basis for evaluating and describing them. Applicable metrics are defined, and an architecture for scalable machines is presented. Two examples illustrate the scalable architecture. Finally, a design parameter based on a mathematical approach is presented to determine the optimal number of modules to be included on a modular scalable machine. This as a design parameter is important because it limits machine size and the number of module interfaces included in the base machine structure.     

Association-Based Active Access Control models with balanced scalability and flexibility

In existing Active Access Control (AAC) models, the scalability and flexibility of security policy specification should be well balanced, especially: (1) authorizations to plenty of tasks should be simplified; (2) team workflows should be enabled; (3) fine-grained constraints should be enforced. To address this issue, a family of Association-Based Active Access Control (ABAAC) models is proposed. In the minimal model ABAAC₀, users are assigned to roles while permissions are assigned to task-role associations. In a workflow case, to execute such an association some users assigned to its component role will be allocated. The association's assigned permissions can be performed by them during the task is running in the case. In ABAAC₁, a generalized association is employed to extract common authorizations from multiple associations. In ABAAC₂, a fine-grained separation of duty (SoD) is enforced among associations. In the maximal model ABAAC₃, all these features are integrated, and similar constraints can be specified more concisely. Using a software workflow, case validation is performed. Comparison with a representative association based AAC model and the most scalable AAC model so far indicates that: (1) enough scalability is achieved; (2) without decomposition of a task, different permissions can be authorized to multiple roles in it; (3) separation of more fine-grained duties than roles and tasks can be enforced.     

Timing analysis of network on chip architectures for MP-SoC platforms

Recently, the use of multiprocessor system-on-chip (MP-SoC) platforms has emerged as an important integrated circuit design trend for high-performance computing applications. As the number of reusable intellectual property (IP) blocks on such platforms continues to increase, many have argued that monolithic bus-based interconnect architectures will not be able to support the clock cycle requirements of these leading-edge SoCs. While hierarchical system integration using multiple smaller buses connected through repeaters or bridges offer possible solutions, such approaches tend to be ad hoc in nature, and therefore, lack generality and scalability. Instead, many different forms of network on chip (NoC) architectures have been proposed in the past few years to specifically address this problem. We believe that the NoC approach will ultimately be the preferred communication fabric for next generation designs. To support this conjecture, this paper demonstrates, through detailed circuit design and timing analysis that different proposed NoC architectures to date are guaranteed to achieve the minimum possible clock cycle times in a given CMOS technology, usually specified in normalized units as 10-15 FO4 delays. This is contrasted with the bus-based approach, which may require several design iterations to deliver the same performance when the number of IP blocks connected to the bus exceeds certain limits.     

Balancing the tradeoffs between scalability and availability in mobile ad hoc networks with a flat hashing-based location service

In this paper, we propose FSLS (Flat-based Some-for-some Location Service), a new location service for ad hoc mobile networks. The location service is based on the hash-based sets system that can offer a high location information availability. The network area is divided into non-overlapping zones. A node identifier is mapped to a set of home zones, each of which contains a unique location server, which makes FSLS works as a some-for-some approach. Using cross-layer design, the service can tolerate server mobility and server failures, and last for a long time period. We analyze FSLS and six other existing location services. The theoretical analysis as well as simulation results show that FSLS offers a good trade-off between location availability and scalability. It comes second after a quorum-based location service in terms of location availability and it is the closest competitor to a hierarchical location service in terms of scalability.