航姿信号的模拟

阐述了航姿信号的特点及其数学表述，着重提出了在仿真系统中模拟产生它们的实用方法。     

用于X射线测厚仪的高压直流电源的设计

为了解决x射线测厚仪管电压纹波系数大,电源稳定度低等问题,设计了一种用于x射线测厚仪的高压直流电源。设计电压为80kV、电流为1mA,系统采用了正负双向倍压整流电路。、测试结果表明,所设计的高压直流电源稳定度高、纹波系数小。     

智能化任意波形V—I—P测量仪的研制

本文介绍了采用模拟乘法器与MCS-51系列8031单片微机相结合的智能型任意波形电压、电流和功率测量仪的软硬件原理。并对仪表的误差及修正方法进行了详细的讨论。     

An iterative logarithmic multiplier

Digital signal processing algorithms often rely heavily on a large number of multiplications, which is both time and power consuming. However, there are many practical solutions to simplify multiplication, like truncated and logarithmic multipliers. These methods consume less time and power but introduce errors. Nevertheless, they can be used in situations where a shorter time delay is more important than accuracy. In digital signal processing, these conditions are often met, especially in video compression and tracking, where integer arithmetic gives satisfactory results. This paper presents a simple and efficient multiplier with the possibility to achieve an arbitrary accuracy through an iterative procedure, prior to achieving the exact result. The multiplier is based on the same form of number representation as Mitchell’s algorithm, but it uses different error correction circuits than those proposed by Mitchell. In such a way, the error correction can be done almost in parallel (actually this is achieved through pipelining) with the basic multiplication. The hardware solution involves adders and shifters, so it is not gate and power consuming. The error summary for operands ranging from 8 bits to 16 bits indicates a very low relative error percentage with two iterations only. For the hardware implementation assessment, the proposed multiplier is implemented on the Spartan 3 FPGA chip. For 16-bit operands, the time delay estimation indicates that a multiplier with two iterations can work with a clock cycle more than 150 MHz, and with the maximum relative error being less than 2%.     

基于AD633模拟鉴相的Q表设计

为解决万用表无法测量Q、D等参数的问题,设计了基于A1D633模拟鉴相的Q表.该测量仪采用DDS芯片AD9851产生正弦激励信号和基准信号,利用高集成度模拟乘法器AD633对信号进行模拟鉴相,并采用差分转换器AD8138对鉴相输出信号进行单端转差分变换,由C8051F060内部自带的ADC对差分信号进行模数转换和数据处理.Q表具有多量程自动切换和LCD实时显示等功能,且体积小、成本低,能满足工程、教学科研测量的需要.     

一种频率精密可调的多波形信号发生器

针对目前信号发生器频率调整困难的缺点，提出了一种利用系数乘法器实现频率精密可调的新方法，并结合单片机、E2PROM以及D／A电路，研制了一个信号频率在1-9999．9Hz范围内，按0．1Hz分辨率变化的多波形信号发生器。     

The regional economic impact of oil and gas extraction in Texas

This paper empirically investigates the regional economic impact of oil and gas extraction in Texas during the recent shale oil boom. Regressions with county-level data over the period 2009–2014 support smaller multiplier effects on local employment and income than corresponding estimates drawn from popular input–output-based studies. Economic impacts were larger for extraction from gas wells than oil wells, while the drilling phase generated comparable impacts. Estimates of economic impacts are greater in a dynamic spatial panel model that allows for spillover effects across local economies as well as over time.     

Reconfigurable Multiplier Blocks: Structures,Algorithm and Applications

This paper presents the efficient design methodology and applications of reconfigurable multiplier blocks (ReMB). ReMB offers significant area, delay and possibly power reduction in time-multiplexed implementation of multiple constant multiplications in many application areas from fixed digital filters, adaptive filters, and filter banks to DFT, FFT and DCT. The reader will be exposed to the fundamental principles of ReMB structures coupled with a novel algorithm for their design as well as illustrative examples where appropriate that help the reader understand the technique in action. The paper also looks into the pros and cons of deploying the technique on standard FPGA platforms as well as discussing the effectiveness of the ReMB approach in custom silicon realization by means of application examples. Area, delay and power (where possible) of the ReMB designs are compared to standard implementations. S.S. Demirsoy now with Altera European Technology Centre, High Wycombe, UK. A. Dempster now with the School of Surveying and Spatial Information Systems, University of New South Wales, Sydney, Australia.     

三种高效快速的量子态滤波和估计优化算法

针对不同干扰和噪声情况下的量子状态估计和滤波问题,分别提出相应的高效量子状态密度矩阵重构凸优化算法.对于稀疏状态干扰和测量噪声同时存在的情况,提出量子状态滤波算法.对分别存在稀疏状态干扰和测量噪声的情况,提出相应两种不同的量子状态估计算法.在5量子位的状态密度矩阵估计仿真实验中分析不同采样率下的3种算法性能.实验表明,3种算法均具有较低的计算复杂度、较快的收敛速度和较低的估计误差.     

A new area-efficient BCD-digit multiplier

In the Internet of Things era, with millions of devices performing financial and commercial operations, decimal arithmetic has become very popular in the computation of many business and commercial applications, in order to maintain decimal rounding and precision. This paper proposes the design and implementation of a new algorithm for decimal multiplication oriented to area reduction. This algorithm is especially suitable for field programmable gate arrays (FPGA) and has thus been implemented on this kind of devices. Results show that the proposed BCD multiplication leads to a significant area reduction without decreasing system performance.