A novel low power hybrid cache using GC-EDRAM cells

In a typical embedded CPU, large on-chip storage is critical to meet high performance requirements. However, the fast increasing size of the on-chip storage based on traditional SRAM cells makes the area cost and energy consumption unsustainable for future embedded applications. Replacing SRAM with DRAM on the CPU’s chip is generally considered not worthwhile because DRAM is not compatible with the common CMOS logic and requires additional processing steps beyond what is required for CMOS. However a special DRAM technology, Gain-Cell embedded-DRAM (GC-eDRAM)  [1], [2], [3] is logic compatible and retains some of the good properties of DRAM (small and low power). In this paper we evaluate the performance of a novel hybrid cache memory where the data array, generally populated with SRAM cells, is replaced with GC-eDRAM cells while the tag array continues to use SRAM cells. Our evaluation of this cache demonstrates that, compared to the conventional SRAM-based designs, our novel architecture exhibits comparable performance with less energy consumption and smaller silicon area, enabling the sustainable on-chip storage scaling for future embedded CPUs.     

USERS' TWO-DIMENSIONAL INTEREST AND ITS STORAGE METHOD

The users' interest can be mined from the web cache and can be used widely. The interest can be specialized by the two-tuple (term, weight) in the simple interest model, in which the association relations are not mined, and then the interest cannot be associated in expressing the users' interest. Based on analyzing the WWW cache model, this letter brings forward a two-dimensional interest model and gives the interrelated methods on how to store the two-dimensional interest model effectively.     

USERS’ TWO-DIMENSIONAL INTEREST AND ITS STORAGE METHOD

The users‘ interest can be mined from the web cache and can be used widely.The interest can be specialized by the two-tuple(term,weight) in the simple interest model,in which the association relations are not mined.and then interest cannot be associated in expressing the users‘interest.Based on analyzing the WWW cache model,this letter brings forward a twodimensional interest model and gives the interrelated methods on how to store the two-dimensional interest model effectively.     

流媒体技术驱动宽带网应用

流媒体技术是宽带网应用的支撑技术，在宽带建设中应用是最关键的，文章从宽带网建设的困惑谈起，详细介绍了流媒体技术的原理、实现方法，最后谈到世界上3家主流公司流媒体产品的基本情况。     

Measuring consistency in TTL-based caches

We propose a general modeling framework to evaluate the performance of cache consistency algorithms. In addition to the usual hit rate, we introduce the hit^* rate as a consistency measure, which captures the fraction of non-stale downloads from the cache. We apply these ideas to the analysis of the fixed TTL consistency algorithm in the presence of network delays. The hit and hit^* rates are evaluated when requests and updates are modeled by renewal processes. Classical results on the renewal function lead to various bounds.     

改善磁盘阵列性能的方法

磁盘阵列是解决计算机Ｉ／Ｏ瓶颈问题的有效方法之一，通过对现有磁盘阵列结构的研究，提出了４种改善磁盘阵列性能的方法，即良分利用磁盘带宽，平衡多盘的负载，减少奇偶检验数据存取时间和磁盘阵列Ｃａｃｈｅ技术等，分析结果表明：在事务处理应用领域，利用Ｃａｃｈｅ来把小写转化为大写可大大改善目前一般情况下，以一道数据大小来作为磁盘的基本存取大小是合适的选择，磁盘阵列负载平衡设计不足是指正常模式下系统请求在多盘间     

Putting it all together – Formal verification of the VAMP

In the verified architecture microprocessor (VAMP) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA. A shorter version of this article with the title “Instantiating uninterpreted functional units and memory system: functional verification of the VAMP” appeared in [8]. The work reported here was done while all the authors were with Saarland University.     

主存技术与时态数据库

多年来，时态数据库的研究与实现受到内存资源的制约。硬件技术的进步为数据库管理系统提供了海量内存。本文提出把时态数据库的全部或大部分数据置于主存中，并能在不读写磁盘的情况下连续作多个事务，称之为时态主存数据库（ＴｅｍｐｏｒａｌＭａｉｎＭｅｍｏｒｙＤＢ，以下简称ＴＭＭＤＢ）。该文讨论了ＴＭＭＤＢ的功能、标准、内存布局、与大缓存ＤＢＭＳ的本质差异，以及由“时态”和“主存”技术结合而引起的一系列特殊问题。     

动态Cache技术在网站性能设计中的应用

本文主要讲述如何利用Cache技术,来有效的提高网站性能。以ASP.NET为基础,展示ASP.NET中使用Cache的新特性,主要应用了Databasedependencies技术。     

基于高速缓存系统的遍历查询研究与设计

由于大型网站具有高负载和高并发的特点,Memcached作为一种解决方案在缓存数据量较大的情况下,使用Memcached的命令组合方式遍历缓存无法完成对所有有效数据的查询。本文针对这个方面研究并设计了缓存数据遍历方案,通过对Memcached客户端的应用研究与模拟实现,很好的解决的这个问题。