一种可支持多路音频、视频同时播放的装置设计

介绍了一种可支持多路音频／视频同时播放的装置,该装置可用来实现电脑或电视等多媒体设备在播放多个视频画面的同时,获得互不干扰的音频输出。该装置中的数据缓存模块连接有多个音频／视频读取模块,音频／视频读取模块的输出端分别与音频输出接口和视频呈现模块连接。     

利用时空背景模型的快速运动目标检测方法

为了弥补运动目标检测中传统混合高斯背景模型仅对单个像素建模、运算耗时的不足,通过提取背景时间统计特征和空间区域特征建立模型,针对模型中的高斯分量采用一种改进的分量个数自适应算法,并在此模型基础上,提出一种自适应迭代分块目标检测方法。通过包含区域信息的背景模型检测目标,减少在同一背景区域中目标的误判和漏判。将自适应迭代分块检测算法与背景的区域信息结合,可以在不降低检测精度的前提下大大提高算法执行速度。实验结果表明,相对于传统算法,本文检测法检测结果信噪比更高,目标更加完整,运行速度平均提高了22%。     

集装箱码头三维仿真组件平台

为直观、形象地研究集装箱码头生产优化问题,采用三维仿真的方法实现集装箱码头物流信息与作业过程的可视化．基于不同业务流程的仿真要求,合理地划分静态布局、装卸设备、装卸对象、码头操作、运动学解算、数据访问、通信接口和图形渲染等组件的粒度;建立层次结构形式的组件平台,体现客观对象的逻辑关系;遵循标准COM＋规范设计岸桥、场桥和集卡等集装箱码头主要三维仿真组件．以上海振华重工（集团）股份有限公司自动化集装箱码头为例验证该组件平台的可操作性,结果表明该方法对集装箱码头装卸工艺的改进和管理水平的提升具有实际指导意义．     

U—Boot在64位多内核MIPS处理器上的移植

介绍了源码开放的通用启动模块U．Boot的文件结构,并以Broadcom公司的4内核处理器BCM1480和RMI的32内核处理器XLR732为例,阐述了该模块在64位多内核MIPS体系结构处理器上的移植经验,包括文件的修改、新增、编译、多内核的启动顺序等。     

Path partitions of hypercubes

A path partition of a graph G is a set of vertex-disjoint paths that cover all vertices of G. Given a set of pairs of distinct vertices of the n-dimensional hypercube Qn, is there a path partition of Qn such that ai and bi are endvertices of Pi? Caha and Koubek showed that for 6m?n, such a path partition exists if and only if the set P is balanced in the sense that it contains the same number of vertices from both classes of bipartition of Qn.In this paper we show that this result holds even for 2m−e<n, where e is the number of pairs of P that form edges of Qn. Moreover, our bound is optimal in the sense that for every n?3, there is a balanced set P in Qn such that 2m−e=n, but no path partition with endvertices prescribed by P exists.     

Achieving accurate and context‐sensitive timing for code optimization

Key computational kernels must run near their peak efficiency for most high‐performance computing (HPC) applications. Getting this level of efficiency has always required extensive tuning of the kernel on a particular platform of interest. The success or failure of an optimization is usually measured by invoking a timer. Understanding how to build reliable and context‐sensitive timers is one of the most neglected areas in HPC, and this results in a host of HPC software that looks good when reported in the papers, but delivers only a fraction of the reported performance when used by actual HPC applications. In this paper, we motivate the importance of timer design and then discuss the techniques and methodologies we have developed in order to accurately time HPC kernel routines for our well‐known empirical tuning framework, ATLAS. Copyright © 2008 John Wiley & Sons, Ltd.     

An LMI approach to synthesis subject to almost asymptotic regulation constraints

A multi-objective controller synthesis problem is considered in which an output is to be regulated approximately by assuring a bound on the steady-state peak amplification in response to an infinite-energy disturbance, while also guaranteeing a desired level of performance measured in terms of the worst-case energy gain from a finite-energy input to a performance output. Relying on a characterization of the controllers with which almost asymptotic regulation is accomplished, the problem of guaranteeing the desired level of performance is reduced to solving a system of linear matrix inequalities subject to a set of linear equality constraints. Based on the solution of this system, a procedure is outlined for the construction of a suitable controller whose order is equal to the order of the plant plus the order of the exogenous system.     

Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors

In glueless shared-memory multiprocessors where cache coherence is usually maintained using a directory-based protocol, the fast access to the on-chip components (caches and network router, among others) contrasts with the much slower main memory. Unfortunately, directory-based protocols need to obtain the sharing status of every memory block before coherence actions can be performed. This information has traditionally been stored in main memory, and therefore these cache coherence protocols are far from being optimal. In this work, we propose two alternative designs for the last-level private cache of glueless shared-memory multiprocessors: the lightweight directory and the SGluM cache. Our proposals completely remove directory information from main memory and store it in the home node’s L2 cache, thus reducing both the number of accesses to main memory and the directory memory overhead. The main characteristics of the lightweight directory are its simplicity and the significant improvement in the execution time for most applications. Its drawback, however, is that the performance of some particular applications could be degraded. On the other hand, the SGluM cache offers more modest improvements in execution time for all the applications by adding some extra structures that cope with the cases in which the lightweight directory fails.     

一种基于有限记忆多LRU的Web缓存替换算法

Web缓存的核心是缓存内容的替换算法.在动态不确定的网络环境下,本文提出一种基于有限记忆的多LRU (LH-MLRU)Web缓存替换算法,它是一种低开销、高性能和适应性的算法.LH-MLRU综合考虑各项因素对Web对象使用多个LRU队列进行分类管理,引入Web对象最近被访问的历史作为缓存内容替换的一个关键因素,来预测对象可能再次被访问的概率.通过周期性的训练参数可以适应动态不确定的网络环境.轨迹驱动的仿真实验表明LH-MLRU在各项性能指标上均优于其他算法,可以显著的提高Web缓存的性能.     

指令优化设计与指令缓存结构相互关系的研究

传统的指令优化方法通常不考虑调整指令高速缓存的硬件体系结构,只能得到局部优化结果.本文以实验的方法研究了指令优化设计和指令缓存配置之间的关系,通过实现程序指令优化并在不同指令缓存配置的平台上运行优化前后的程序,对比缓存缺失率,为进一步提高指令缓存性能提供了重要参考.实验结果表明指令缓存配置对指令优化的性能有极大的影响,在系统设计阶段同时考虑指令优化和指令缓存结构将能大幅度地改进指令缓存的性能.