Substrate noise isolation improvement in a single-well standard CMOS process

This work describes a fully CMOS compatible methodology, which makes available a pseudo deep n-well in single-well standard CMOS process. The proposed method is based on mask manipulation to accommodate the field implant p-type region into the n-well, and does not require any additional masks or modification in the CMOS process flow. According to the experimental results, the floating NMOS made available by the methodology shows a reduction in the threshold voltage, which implies a slight improvement in its performance, when compared with its standard NMOS counterpart. It was also experimentally demonstrated up to 3 GHz, that the guard-ring field implant/pseudo deep n-well proposed structure improves substrate noise isolation when compared to the classical p+ guard-ring, with a maximum improvement above 20 dB for low frequencies and a minimum of 4 dB at 3 GHz.     

Fabrication of Superjunction Trench Gate Power MOSFETs Using BSG‐Doped Deep Trench of p‐Pillar

In this paper, we propose a superjunction trench gate MOSFET (SJ TGMOSFET) fabricated through a simple p pillar forming process using deep trench and boron silicate glass doping process technology to reduce the process complexity. Throughout the various boron doping experiments, as well as the process simulations, we optimize the process conditions related with the p pillar depth, lateral boron doping concentration, and diffusion temperature. Compared with a conventional TGMOSFET, the potential of the SJ TGMOSFET is more uniformly distributed and widely spread in the bulk region of the n drift layer due to the trenched p‐pillar. The measured breakdown voltage of the SJ TGMOSFET is at least 28% more than that of a conventional device.     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

3300V 4H-SiC MOSFET 设计与加工

成功设计并制造了击穿电压超过3300V 的4H-SiC MOSFET。通过数字仿真优化了漂移层和DMOSFET有源区参数。漂移层N型外延厚度为33微米并且掺杂浓度为2.5E15cm-3。器件采用浮空场限制环作为终端。当栅极电压为20V,漏极电压为2.5V时,漏极电流为5A。     

一种改进的深亚微米MOSFET噪声模型

提出一种基于小信号的噪声模型,在精确提取0.13 μm MOSFET的小信号参数后,结合Pospieszalsik和pucel模型,运用噪声相关矩阵转换技术提取出所有噪声参数。利用ADS建立噪声模型,在2～20 GHz频率范围内,仿真结果与测量结果吻合良好,验证了模型的准确性。     

适用于电动汽车的SiC MOSFET PSpice仿真模型研究

为了基于PSpice电路对电动汽车DC/DC变换器中的碳化硅(SiC)MOSFET的工作特性进行实时准确地仿真,针对SiC MOSFET提出了一种新型的电压控制电流源型VCCST(voltage-controlled current source type)PSpice仿真模型。首先,为了获得SiC MOSFET准确的静态特性建立了电压控制电流源作为SiC MOSFET的内核,以描述SiC MOSFET的转移特性和输出特性;然后,为了获得SiC MOSFET准确的动态特性,建立了基于电压控制电流源与恒定电容的栅漏电容(CGD)子电路模型,所提SiC MOSFET VCCST PSpice模型在简化参数提取方法的同时,能够满足模型准确性的要求;最后,建立的SiC MOSFET VCCST PSpice模型应用于Boost变换器进行仿真和实验,并对SiC MOSFET的特性进行测试。测试结果验证了所提SiC MOSFET VCCST PSpice仿真模型的准确性和实时性,从而为SiC MOSFET在电动汽车DC/DC变换器中的设计和应用提供了便利。     

SiC MOSFET在航空静止变流器中的应用研究

航空静止变流器实现机载直流电到交流电的转换,对功率密度、效率、环境适应性、可靠性和电气性能等有较高的要求。碳化硅(SiC)半导体器件的开关速度快、高温特性好,在航空静止变流器中有很好的应用前景,但目前关于宽禁带器件在航空静止变流器中应用的研究比较少。首先结合现有的典型航空静止变流器电路拓扑分析了SiC MOSFET应用的关键问题;然后针对航空静止变流器逆变级的两级级联半桥逆变器,对比分析了应用SiC MOSFET与Si MOSFET的损耗大小,分析结果表明在现采用的开关频率下,即使现有SiC MOSFET导通损耗较大,但总损耗仍较小;且开关频率越高,SiC MOSFET的效率优势越明显,最后为适应高开关频率SiC MOSFET逆变器的需要设计了一种适应高开关频率和宽占空比变化信号的SiC MOSFET驱动电路,搭建了1台500 VA、115 V/400 Hz两级级联半桥逆变器实验样机,并验证了应用SiC MOSFET的航空静止变流器逆变级的可行性。     

SiC MOSFET特性及其应用的关键技术分析

SiC MOSFET(silicon carbide metal-oxide-semiconductor field-effect transistor)以其优越的特性受到国内外学者的广泛关注,采用SiC器件的变换器能够采用高的开关频率、适应高温工作,实现高的功率密度,在一些应用场合能够代替Si基高频开关器件而显著提高电能变换装置的性能。然而,SiC器件与Si器件存在较大的差异,在实际应用中直接替换使用会存在诸多的问题,例如提高工作频率后产生的桥臂串扰、电磁干扰EMI(electromagnetic interference)等问题。目前已有大量关于SiC MOSFET应用研究的文献,但大部分都是针对SiC MOSFET应用中个别问题的研究,尚缺少对SiC MOSFET应用研究成果的系统性归纳与总结的文献。首先基于对SiC MOSFET与Si MOSFET/IGBT(insulated gate bipolar transistor)的静态、动态特性的对比,总结出SiC MOSFET在实际应用中需要关注的重点特性;然后从SiC MOSFET建模、驱动电路设计、EMI抑制以及拓扑与控制方式的选择等方面对已有的研究成果进行归纳与评述;最后指出了SiC MOSFET在应用中所需要研究解决的关键问题。     

功率MOSFET寿命模型综述

MOSFET是实现电力电子装置功能的核心器件,但其寿命短是制约电力电子系统可靠性的关键因素。由老化造成的MOSFET失效分为封装失效和参数漂移失效,前者由MOSFET制造工艺及材料导致的缺陷在工作环境中恶化而产生,后者为器件在使用过程中其内部微观退化机制在宏观参数的体现。对目前已有的MOSFET寿命相关的研究成果进行总结,分析了MOSFET的各类失效模式,并建立了各类失效模式下MOSFET寿命模型;并进一步总结了各类失效模式下寿命模型的失效判据及其各类寿命预测模型实验验证方法。     

Characteristics of GdGaO grown by MBE

Ga₂O₃/GdGaO dielectric stacks have been grown on GaAs for MOSFETs. This paper highlights variations in the characteristics of GdGaO as the Gd flux, Ga₂O flux and substrate temperature are changed. The growth rate, composition, crystallinity are discussed and the sheet resistance of final MOSFET structures are presented. The Gd compositional variation with depth is examined using Rutherford back scattering (RBS) and electron energy loss spectroscopy (EELS).