关于提高变频器调频速度的研究

本文介绍了作者的一项专利技术。对于需要比较快速、比较频繁地调整变频器频率应用场合,目前的通用变频器就很难满足这个需要,尤其是在大惯性负载上使用变频器时,须将升、降频（特别是降频）速度设置的比较慢,以适应由于惯性造成的电机转速的滞后。本专利技术克服上述传统变频器目前存在的缺陷,在传统变频器上增加比较简单并业已成熟的换相技术,为变频器的制造提供了一种新的附加技术。     

一种用于高速锁相环的新型CMOS电荷泵电路

提出了一种适用于高速锁相环电路的新型CMOS电荷泵电路。该电路利用正反馈电路提高电荷泵的转换速度，利用高摆幅镜像电流电路提高输出电压的摆动幅度，消除了电压跳变现象。电路设计和H-SPICE仿真基于BL 1．2μm工艺BSIM3、LEVEL=47的CMOS库，电源电压为2V，功耗为0．1mW。仿真结果表明，该电路可以很好地应用于高速锁相环电路。     

Analysis of alternating current driven electroluminescence in organic light emitting diodes: A comparative study

The alternating current (AC) responses of double-injection and double-insulated organic light-emitting diodes (OLEDs) were investigated and compared. To reveal the electroluminescent (EL) processes in these devices, the AC voltage and frequency dependence of the EL intensity and capacitive current were studied in the time domain with a focus on phase difference analysis. It was found that the voltage-dependent transit time and frequency-dependent carrier distribution were important for the AC-driven performance of the double-injection OLEDs. In contrast, although the double-insulated OLEDs shared some similarities with the double-injection OLEDs, they had some unique characteristics, which were the absence of resistive current and phase shift of EL profiles. It was revealed that the EL in the double-insulated OLEDs was driven by the displacement current generated by the ionization of the doped layers, which, however, formed space charge regions and undermined the EL emission. The space charge redistributed the electric field across the devices after the initiation of EL, making the EL maintain for a limited time interval. This effect was significant under low frequency and high AC voltage. Comparing the phase difference between both devices, it was indicated that the space charge effect was responsible for the observed EL phase shift and the asymmetric EL profiles at low frequency and high AC voltage in the double-insulated OLEDs. The proposed model was also of help to understand the EL saturation phenomena with AC frequency and voltage in those devices.     

基于交互式多模型的弹道导弹跟踪

弹道导弹飞行主动段和自由段的运动学模型差别很大,在未准确知道导弹关机点时间先验信息前提下如何对弹道导弹主动段到自由段进行连续跟踪已成为目前亟待解决的问题.针对该问题,提出了一种实时交互多模型跟踪算法,根据弹道导弹主动段和自由段不同受力情况建立相应的跟踪模型.该算法包括两个滤波器:一个为对主动段跟踪效果比较好的CA-EK...     

A low phase noise and low spur PLL with auto frequency control circuit for L1-band GPS receiver

A low phase noise and low spur phase-locked loop (PLL) for L1-band global positioning system receiver is proposed in this paper. For obtaining low phase noise for PLL, All-PMOS LC-VCO with varactor-smoothing technique and noise-filtering technique is adopted. To reduce the reference spur, a low current-mismatch charge pump is carefully designed. A quasi-closed-loop auto frequency control circuit is used to accelerate the lock process of PLL. The PLL is fabricated in 180 nm CMOS Mixed-Signal process while it operates under 1.8 V supply voltage. The measured output frequency of PLL is 1.571 GHz and output power is −1.418 dBm. The in-band phase noise is −98.1 dBc/Hz @ 100 kHz, while the out-band phase noise is −130.3 dBc/Hz @ 1 MHz. The reference spur is −75.8 dBc at 16.368 MHz offset. When quasi closed-loop AFC is working, the measured lock time is about 10.2 μs.     

Fast locking,startup-circuit free,low area, 32-phase analog DLL

This work presents 32-phase analog delay-locked-loop (DLL) having fast locking ability, startup-circuit free operation, and a low area with improved DNL-INL performance. The proposed faster delay-cell and the new bias-circuit enable startup-circuit free operation under process-voltage-temperature (PVT) variation, while the DLL achieves low area and faster locking by using a small filter capacitor. Again, input and output clocks pass through the respective CMOS buffer before the phase detector (PD) for load matching, which reduces DNL-INL in the DLL. The analog DLL locks in less than 54 or 56 clock cycles depending upon initial control voltage (supply or ground voltage) with 100 MHz input clock. The DLL generates 32-phase clocks with a bin-size of 312.5 ps, the peak-to-peak period jitter of 9.51 ps, the rms period jitter of 1.36 ps, the phase-offset error of 4.72 ps, DNL and INL less than ±0.11 LSB. The design consumes 3.54 mW power with a supply voltage of 3.3 V, and an area of 0.017 mm² in UMC 180 nm MMRF technology. ^© 2001 Elsevier Science. All rights reserved     

基于符号频域均衡的CPM迭代检测算法

该文研究了部分响应连续相位调制(CPM)信号的频域均衡技术,设计了一种新的发射信号帧结构,并在此基础上提出了一种低复杂度的CPM迭代检测算法,分析了该迭代检测算法的复杂度和误码性能。理论分析和仿真结果表明,在多径衰落信道下,该算法比已有的CPM双迭代频域均衡算法具有更低的复杂度和更好的性能。     

天线相位中心暗室标定法远场条件研究

将有限测试距离引入的测相误差公式由一维辐射源拓展到二维口径辐射源.与传统相位方向图误差分析中只考虑单一方向上测相绝对误差的方法不同,提出全新的基于保证有限测试距离处不同方向相位差与远场相位差一致的有限测试距离相位中心测量误差分析方法.利用文献[6]的天线相位中心暗室测量方法,对有限距离引入的误差进行了数值分析,从而得到满足一定精度要求的远场测量条件.以实际天线相位中心标定例子说明了分析方法的正确性.     

KNbO_3:Fe自泵相位共轭

本文提出KNbO_3:Fe光折变晶体的异形切割和最佳实验配置,首次在室温下获得内环腔自泵相位共轭,反射率高达～60％。     

数字调谐系统在组合音响上的应用

本文介绍了NEC公司大规模专用集成电路μPD1715G——016及其在组合音响上的应用,讨论了设计中的几点关键性问题,并分析了解决问题的方法和途径。