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81.
The discontinuous Galerkin (DG) methods provide a high-order extension of the finite volume method in much the same way as high-order or spectral/hp elements extend standard finite elements. However, lack of inter-element continuity is often contrary to the smoothness assumptions upon which many post-processing algorithms such as those used in visualization are based. Smoothness-increasing accuracy-conserving (SIAC) filters were proposed as a means of ameliorating the challenges introduced by the lack of regularity at element interfaces by eliminating the discontinuity between elements in a way that is consistent with the DG methodology; in particular, high-order accuracy is preserved and in many cases increased. The goal of this paper is to explicitly define the steps to efficient computation of this filtering technique as applied to both structured triangular and quadrilateral meshes. Furthermore, as the SIAC filter is a good candidate for parallelization, we provide, for the first time, results that confirm anticipated performance scaling when parallelized on a shared-memory multi-processor machine.  相似文献   
82.
Crowdsourcing contests have become increasingly important and prevalent with the ubiquity of the Internet. Designing efficient crowdsourcing contests is not possible without the deep understanding of the factors affecting individuals’ continuous participation and their performance. Prior studies have mainly focused on identifying the effect of task-specific, environment-specific, organisation-specific, and individual-specific factors on individuals’ performance in crowdsourcing contests. And to our knowledge, there are no or very few studies on evaluating the effect of individuals’ participation history on their performance. This paper aims to address this research gap using a data set from TopCoder. This study derives competitors’ participation history factors, such as participation frequency, participation recency, winning frequency, winning recency, tenure, and last performance to construct models depicting effects of these factors on competitors’ performance in online crowdsourcing contests. The research findings demonstrate that most of competitors’ participation history factors have significant effect on their performance. This paper also indicates that competitors’ participation frequency and winning frequency moderate the relationship between last performance and performance, and relationship between tenure and performance positively. On the other hand, individuals’ participation recency and winning recency moderate relationship between last performance and performance negatively, but have no significant effect on the relationship between tenure and performance.  相似文献   
83.
Pancreatic β-cell-specific clock knockout mice develop β-cell oxidative-stress and failure, as well as glucose-intolerance. How inflammatory stress affects the cellular clock is under-investigated. Real-time recording of Per2:luciferase reporter activity in murine and human pancreatic islets demonstrated that the proinflammatory cytokine interleukin-1β (IL-1β) lengthened the circadian period. qPCR-profiling of core clock gene expression in insulin-producing cells suggested that the combination of the proinflammatory cytokines IL-1β and interferon-γ (IFN-γ) caused pronounced but uncoordinated increases in mRNA levels of multiple core clock genes, in particular of reverse-erythroblastosis virus α (Rev-erbα), in a dose- and time-dependent manner. The REV-ERBα/β agonist SR9009, used to mimic cytokine-mediated Rev-erbα induction, reduced constitutive and cytokine-induced brain and muscle arnt-like 1 (Bmal1) mRNA levels in INS-1 cells as expected. SR9009 induced reactive oxygen species (ROS), reduced insulin-1/2 (Ins-1/2) mRNA and accumulated- and glucose-stimulated insulin secretion, reduced cell viability, and increased apoptosis levels, reminiscent of cytokine toxicity. In contrast, low (<5,0 μM) concentrations of SR9009 increased Ins-1 mRNA and accumulated insulin-secretion without affecting INS-1 cell viability, mirroring low-concentration IL-1β mediated β-cell stimulation. Inhibiting nitric oxide (NO) synthesis, the lysine deacetylase HDAC3 and the immunoproteasome reduced cytokine-mediated increases in clock gene expression. In conclusion, the cytokine-combination perturbed the intrinsic clocks operative in mouse and human pancreatic islets and induced uncoordinated clock gene expression in INS-1 cells, the latter effect associated with NO, HDAC3, and immunoproteasome activity.  相似文献   
84.
An ongoing trend in datacom switches is to require optical transceivers to be smaller and have lower power dissipation in order to enable greater port densities. The transition from 1 GE to 10 GE was unusually slow for the Ethernet market due in part to the high cost. high power dissipation, and form factor of the optical module. The industry is now overcoming these hurdles with the transition to SFP + modules, which will enable more traditional Ethernet growth. Upcoming 40 GE and 100 GE are multilane protocols, presenting even greater challenges than 10 GE laced at its inception, potentially slowing their adoption. Leveraging SFP+ class technology such as simple EDC capabilities can lower cost and reduce module form factors, thus accelerating the transition to 40/100 GE interlace deployment.  相似文献   
85.
Optimization of operational conditions for the polymerization of propylene with Ziegler–Natta catalyst was carried out via RSM. Response surface methodology (RSM) based on a three-level, four-variable Box–Behnken design was used to evaluate the interactive effects of reaction conditions such as reaction temperature (60–80 °C), monomer pressure (5–8 bar), hydrogen volume (130–170 mL), and cocatalyst to catalyst ratio (Al/Ti, 340–500) on the catalyst activity and melt flow rate (MFR). The optimum reaction conditions derived via RSM were: temperature 70 °C, pressure 8 bar, hydrogen volume 151 mL, and cocatalyst to catalyst ratio 390. The experimental catalyst activity and MFR were 8 g polypropylene/mg catalyst and 10.9 g/10 min, respectively, under optimum conditions. Optimum values were determined from process cost point of view and offered better operational conditions.  相似文献   
86.
The continued downscaling of CMOS technology has resulted in very high performance devices, but power dissipation is a limiting factor on this way. Power and performance of a device are dependent on process, temperature, and workload variation that makes it impossible to find a single power optimal design. As a result, adaptive power and performance adjustment techniques emerged as attractive methods to improve the effective power efficiency of a device in modern design approaches. Focusing on this issue, in this paper, a novel logic family is proposed that enables tuning the transistor's effective threshold voltage after fabrication for higher speed or lower power. This method along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the workload requirement. The externally static topology of the proposed logic makes it possible to replace static circuits without requiring significant changes in the system. Experimental results obtained using 90‐nm CMOS standard technology show that the proposed logic improves the average power‐delay product by about 40% for the attempted benchmarks.  相似文献   
87.
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