软件无线电及其实现技术

软件无线电是一种新兴技术，通过软件使多种业务、多种标准、多个频段与灵活的无线电系统的组合成为可重新配置和可重新编程的。介绍了软件无线电的概念及系统结构，并进一步讨论了现阶段软件无线电所面临的技术问题以及相应的实现方案。     

轻质莫来石浇注料及其在轧钢加热炉上的应用

介绍了轻质莫来石骨料及用该骨料配制的轻质莫来石浇注料的性能，并介绍了该浇注料在轧钢加热炉上的应用情况。     

Investigation and modeling of stress effects on the formation of cobalt salicide

This letter studies resistance variations of the Co salicide interconnect accompanied by various surrounding in a sub-0.13-/spl mu/m CMOS technology. Our analysis shows that, during the salicidation processes, the diffusion of Co atoms and thus salicide thickness and forms of Co salicide layer are greatly affected by the stresses from surrounding structures. Moreover, variations in resistance among the various structures could exceed 100%. Thus, these stress effects were analyzed in detail based on transmission electron microscopy micrographs of Co salicide layers accompanied by four different surrounding structures.     

用于千兆以太网模拟接收前端的预均衡电路

文章采用0．18μm／3．3V 1P6M标准CMOS工艺设计实现了用于千兆(1000BaseT)以太网模拟接收前端的预均衡电路。电路由基带漂移补偿电路和可变增益放大器两部分组成，基带漂移补偿电路补偿了由于变压器的高通特性引起的信号基带漂移现象。调整范围从1．75V到2．25V。可变增益放大器除了具有变化范围从1．3到5、共15档的常规增益可调功能外。还具有带宽65MHz的低通滤波特性和共5档的高频补偿功能，版图后仿真结果表明所设计电路完全达到了千兆以太网的系统要求，很好地实现了对输入信号的模拟预均衡处理。     

基于CORDIC的一种高速实时定点FFT的FPGA实现

本文论述了一种利用CORDIC算法在FPGA上实现高速实时定点FFF的设计方案。利用CORDIC算法来实现复数乘法，与使用乘法器相比降低了系统的资源占用率，提高了系统速度[1]。设计基于基4时序抽取FFT算法，采用双端口内置RAM和流水线串行工作方式。本设计针对256点、24位长数据进行运算，在XilnxSpartan2E系列的xc2s300e器件下载验证通过，完成一次运算约为12μs，可运用于高速DSP、数字签名算法等对速度要求高的领域。     

The Grand Pareto: A Methodology for Identifying and Quantifying Yield Detractors in Volume Semiconductor Manufacturing

A method of communicating a unified pareto, we call "Grand Pareto," for technology-wide failure mechanisms that limit the profitability of a fabrication facility is presented. The Grand Pareto leverages multiple defect detection and isolation techniques in conjunction with state-of-the-art physical failure analysis and statistical yield analysis techniques to create a single message for the process community to drive the yield improvement efforts. The methodology has been successfully deployed at IBM where it has been assisting identification of key yield detractors for several high-end microprocessors in volume production     

Using Nonadditive Fuzzy Integral to Assess Performances of Organizational Transformation Via Communities of Practice

Organizational transformations have been widely adopted by firms who wish to improve their competitive advantage to be better prepared to face external challenges. This research has chosen Communities of Practice (CoPs) as the subject of discussion for an assessment model to reform organizations that undertake CoPs for collective knowledge to enhance their core competencies. Given the interrelationships between criteria, this research uses the nonadditive fuzzy integral to develop a framework for the CoPs performance assessment. The purposes of this paper are to identify the key dimensions/criteria in the CoPs, to use fuzzy logic method to analyze the relative importance of each criterion, and to rank the criteria so that proper resources can be allocated while managing the CoPs. Through interviews with experts, four strategy alternatives and 16 criteria along four dimensions are generated. A survey of the CoPs practitioners is then conducted to compare the results of each criterion. The results will not only help organizations that intend to initiate changes via the CoPs activities to decide the ranking of their appraisal criteria, but it can also assist them in guiding the behavior of their staff while effectively monitoring and improving the performances of the CoPs     

Fitted Elmore delay: a simple and accurate interconnect delay model

In this brief, we present a new interconnect delay model called fitted Elmore delay (FED). FED is generated by approximating HSPICE delay data using a curve fitting technique. The functional form used in curve fitting is derived based on the Elmore delay (ED) model. Thus, our model has all the advantages of the ED model. It has a closed-form expression as simple as the ED model and is extremely efficient to compute. Interconnect optimization with respect to design parameters can also be done as easily as in the ED model. In fact, most previous algorithms and programs based on ED model can use our model without much change. Most importantly, FED is significantly more accurate than the ED model. The maximum error in delay estimation is at most 2% for our model, compared to 8.5% for the scaled ED model. The average error is less than 0.8%. We also show that FED can be more than 10 times more accurate than the ED model when applied to wire sizing.