Preparation of Ga_2O_3 thin film solar-blind photodetectors based on mixed-phase structure by pulsed laser deposition

Gallium oxide(Ga_2O_3) thin films were deposited on a-Al2O3(1120) substrates by pulsed laser deposition(PLD) with different oxygen pressures at 650?C. By reducing the oxygen pressure, mixed-phase Ga_2O_3 films with α and β phases can be obtained, and on the basis of this, mixed-phase Ga_2O_3 thin film solar-blind photodetectors(SBPDs) were prepared.Comparing the responsivities of the mixed-phase Ga_2O_3 SBPDs and the single β-Ga_2O_3 SBPDs at a bias voltage of 25 V,it is found that the former has a maximum responsivity of approximately 12 A/W, which is approximately two orders of magnitude larger than that of the latter. This result shows that the mixed-phase structure of Ga_2O_3 thin films can be used to prepare high-responsivity SBPDs. Moreover, the cause of this phenomenon was investigated, which will provide a feasible way to improve the responsivity of Ga_2O_3 thin film SBPDs.     

Growth of β-Ga_2O_3 Films on Sapphire by Hydride Vapor Phase Epitaxy

Two-inch Ga_2O_3 films with(ˉ201)-orientation are grown on c-sapphire at 850–1050°C by hydride vapor phase epitaxy. High-resolution x-ray diffraction shows that pure β-Ga_2O_3 with a smooth surface has a higher crystal quality, and the Raman spectra reveal a very small residual strain in β-Ga_2O_3 grown by hydride vapor phase epitaxy compared with bulk single crystal. The optical transmittance is higher than 80% in the visible and near-UV regions, and the optical bandgap energy is calculated to be 4.9 e V.     

Characterization of vertical Au/β-Ga_2O_3 single-crystal Schottky photodiodes with MBE-grown high-resistivity epitaxial layer

High-resistivity β-Ga_2O_3 thin films were grown on Si-doped n-type conductive β-Ga_2O_3 single crystals by molecular beam epitaxy(MBE).Vertical-type Schottky diodes were fabricated,and the electrical properties of the Schottky diodes were studied in this letter.The ideality factor and the series resistance of the Schottky diodes were estimated to be about1.4 and 4.6×10~6 Ω.The ionized donor concentration and the spreading voltage in the Schottky diodes region are about4×10~(18)cm~(-3) and 7.6 V,respectively.The ultra-violet(UV) photo-sensitivity of the Schottky diodes was demonstrated by a low-pressure mercury lamp illumination.A photoresponsivity of 1.8 A/W and an external quantum efficiency of8.7 ×10~2%were observed at forward bias voltage of 3.8 V,the proper driving voltage of read-out integrated circuit for UV camera.The gain of the Schottky diode was attributed to the existence of a potential barrier in the i-n junction between the MBE-grown highly resistive β-Ga_2O_3 thin films and the n-type conductive β-Ga_2O_3 single-crystal substrate.     

High performance lateral Schottky diodes based on quasi-degenerated Ga_2O_3

Ni/β-Ga_2 O_3 lateral Schottky barrier diodes(SBDs) were fabricated on a Sn-doped quasi-degenerate n~+-Ga_2 O_3(201)bulk substrate. The resultant diodes with an area of 7.85 ×10~(-5) cm~2 exhibited excellent rectifying characteristics with an ideality factor of 1.21, a forward current density(J) of 127.4 A/cm2 at 1.4 V, a specific on-state resistance(R_(on,sp)) of1.54 mΩ·cm~2,and an ultra-high on/off ratio of 2.1 ×10~(11) at±1 V. Due to a small depletion region in the highly-doped substrate, a breakdown feature was observed at-23 V, which corresponded to a breakdown field of 2.1 MV/cm and a power figure-of-merit(VB2/R_(on)) of 3.4×10~5 W/cm~2. Forward current-voltage characteristics were described well by the thermionic emission theory while thermionic field emission and trap-assisted tunneling were the dominant transport mechanisms at low and high reverse biases, respectively, which was a result of the contribution of deep-level traps at the metal-semiconductor interface. The presence of interfacial traps also caused the difference in Schottky barrier heights of 1.31 eV and 1.64 eV respectively determined by current-voltage and capacitance-voltage characteristics. With reduced trapping effect and incorporation of drift layers, the β-Ga_2 O_3 SBDs could further provide promising materials for delivering both high current output and high breakdown voltage.     

Charge trapping memory device based on the Ga_2O_3 films as trapping and blocking layer

We present a new charge trapping memory(CTM) device with the Au/Ga_2O_3/SiO_2/Si structure, which is fabricated by using the magnetron sputtering, high-temperature annealing, and vacuum evaporation techniques. Transmission electron microscopy diagrams show that the thickness of the SiO_2 tunneling layer can be controlled by the annealing temperature.When the devices are annealed at 760℃, the measured C–V hysteresis curves exhibit a maximum 6 V memory window under a ±13 V sweeping voltage. In addition, a slight degradation of the device voltage and capacitance indicates the robust retention properties of flat-band voltage and high/low state capacitance. These distinctive advantages are attributed to oxygen vacancies and inter-diffusion layers, which play a critical role in the charge trapping process.     

Investigation of β-Ga_2O_3 films and β-Ga_2O_3/GaN heterostructures grown by metal organic chemical vapor deposition

In this work,(-201) β-Ga_2O_3 films are grown on GaN substrate by metal organic chemical vapor deposition(MOCVD). It is revealed that the β-Ga_2O_3 film grown on GaN possesses superior crystal quality, material homogeneity and surface morphology than the results of common heteroepitaxial β-Ga_2O_3 film based on sapphire substrate. Further, the relevance between the crystal quality of epitaxial β-Ga_2O_3 film and the β-Ga_2O_3/GaN interface behavior is investigated. Transmission electron microscopy result indicates that the interface atom refactoring phenomenon is beneficial to relieve the mismatch strain and improve the crystal quality of subsequent β-Ga_2O_3 film. Moreover, the energy band structure of β-Ga_2O_3/GaN heterostructure grown by MOCVD is investigated by X-ray photoelectron spectroscopy and a large conduction band offset of 0.89 eV is obtained. The results in this work not only convincingly demonstrate the advantages of β-Ga_2O_3 films grown on GaN substrate, but also show the great application potential of MOCVD β-Ga_2O_3/GaN heterostructures in microelectronic applications.     

Study on nitridation processes of β-Ga_2O_3 single crystal

Nitridatedβ-Ga_2O_3(100)substrate was investigated as the substrate for GaN epitaxial growth.The effects of nitridation temperature and surface roughness ofβ-Ga_2O_3 wafers on the formation of GaN were studied.It was found that the most optimized nitridation temperature was 900°C,and hexagonal GaN with preferred orientation was produced on the well-polished wafer.The nitridation mechanism was also discussed.     

Device topological thermal management of β-Ga_2O_3 Schottky barrier diodes

The ultra-wide bandgap semiconductor β gallium oxide(β-Ga_2 O_3) gives promise to low conduction loss and high power for electronic devices. However, due to the natural poor thermal conductivity of β-Ga_2 O_3, their power devices suffer from serious self-heating effect. To overcome this problem, we emphasize on the effect of device structure on peak temperature in β-Ga_2 O_3 Schottky barrier diodes(SBDs) using TCAD simulation and experiment. The SBD topologies including crystal orientation of β-Ga_2 O_3, work function of Schottky metal, anode area, and thickness, were simulated in TCAD, showing that the thickness of β-Ga_2 O_3 plays a key role in reducing the peak temperature of diodes. Hence, we fabricated β-Ga_2 O_3 SBDs with three different thickness epitaxial layers and five different thickness substrates. The surface temperature of the diodes was measured using an infrared thermal imaging camera. The experimental results are consistent with the simulation results. Thus, our results provide a new thermal management strategy for high power β-Ga_2 O_3 diode.     

Degradation of β-Ga_2O_3 Schottky barrier diode under swift heavy ion irradiation

The electrical characteristics and microstructures of β-Ga_2 O_3 Schottky barrier diode(SBD) devices irradiated with swift heavy ions(2096 Me V Ta ions) have been studied. It was found that β-Ga_2 O_3 SBD devices showed the reliability degradation after irradiation, including turn-on voltage Von, on-resistance Ron, ideality factor n, and the reverse leakage current density Jr. In addition, the carrier concentration of the drift layer was decreased significantly and the calculated carrier removal rates were 5 × 10~6–1.3 × 10~7 cm~(-1). Latent tracks induced by swift heavy ions were observed visually in the whole β-Ga_2 O_3 matrix. Furthermore, crystal structure of tracks was amorphized completely. The latent tracks induced by Ta ions bombardments were found to be the reason for the decrease in carrier mobility and carrier concentration. Eventually,these defects caused the degradation of electrical characteristics of the devices. In terms of the carrier removal rates, theβ-Ga_2 O_3 SBD devices were more sensitive to swift heavy ions irradiation than Si C and Ga N devices.     

Preparation and NO_2-gas sensing property of individual β-Ga_2O_3 nanobelt

Monoclinic gallium oxide (β-Ga_2O_3) nanobelts are synthesized from gallium and oxygen by thermal evaporation in an argon atmosphere and their NO_2 sensing properties are studied at room temperature.Electron microscopy studies show that the nanobelts have breadths ranging from 30 to 50 nm and lengths up to tens of micrometers.Both the x-ray diffraction (XRD) and the selected are electron diffraction (SAED) examinations indicate that β-Ga_2O_3 nanobelts have grown into single crystals.Room temperature NO_2 sensing tests show that the current of individual β-Ga_2O_3 nanobelt decreases quickly,and then gently when the NO_2 concentration increases from low to high.It is caused by the NO_2 molecule chemisorption and desorption processes in the surface of β-Ga_2O_3 nanobelt.     

Study on the nitridation of β-Ga_2O_3 films

Single-crystal GaN layers have been obtained by nitriding β-Ga_2O_3 films in NH_3 atmosphere. The effect of the temperature and time on the nitridation and conversion of Ga_2O_3 films have been investigated. The nitridation process results in lots of holes in the surface of films. The higher nitridation temperature and longer time can promote the nitridation and improve the crystal quality of GaN films. The converted Ga N porous films show the single-crystal structures and lowstress, which can be used as templates for the epitaxial growth of high-quality GaN.     

Electronic structures and optical properties of Si-and Sn-doped β-Ga_2O_3: A GGA+U study

The electronic structures and optical properties of β-Ga_2O_3 and Si-and Sn-doped β-Ga_2O_3 are studied using the GGA + U method based on density functional theory. The calculated bandgap and Ga 3d-state peak of β-Ga_2O_3 are in good agreement with experimental results. Si-and Sn-doped β-Ga_2O_3 tend to form under O-poor conditions, and the formation energy of Si-doped β-Ga_2O_3 is larger than that of Sn-doped β-Ga_2O_3 because of the large bond length variation between Ga–O and Si–O. Si-and Sn-doped β-Ga_2O_3 have wider optical gaps than β-Ga_2O_3, due to the Burstein–Moss effect and the bandgap renormalization effect. Si-doped β-Ga_2O_3 shows better electron conductivity and a higher optical absorption edge than Sn-doped β-Ga_2O_3, so Si is more suitable as a dopant of n-type β-Ga_2O_3, which can be applied in deep-UV photoelectric devices.     

Three-dimensional vertical ZnO transistors with suspended top electrodes fabricated by focused ion beam technology

Three-dimensional(3D)vertical architecture transistors represent an important technological pursuit,which have distinct advantages in device integration density,operation speed,and power consumption.However,the fabrication processes of such 3D devices are complex,especially in the interconnection of electrodes.In this paper,we present a novel method which combines suspended electrodes and focused ion beam(FIB)technology to greatly simplify the electrodes interconnection in 3D devices.Based on this method,we fabricate 3D vertical core-double shell structure transistors with ZnO channel and Al₂O₃ gate-oxide both grown by atomic layer deposition.Suspended top electrodes of vertical architecture could be directly connected to planar electrodes by FIB deposited Pt nanowires,which avoid cumbersome steps in the traditional 3D structure fabrication technology.Both single pillar and arrays devices show well behaved transfer characteristics with an Ion/Ioff current ratio greater than 106 and a low threshold voltage around 0 V.The ON-current of the 2×2 pillars vertical channel transistor was 1.2μA at the gate voltage of 3 V and drain voltage of 2 V,which can be also improved by increasing the number of pillars.Our method for fabricating vertical architecture transistors can be promising for device applications with high integration density and low power consumption.     

Effect of the annealing temperature on the long-term thermal stability of Pt/Si/Ta/Ti/4H–SiC contacts

The Pt/Si/Ta/Ti multilayer metal contacts on 4H–Si C are annealed in Ar atmosphere at 600°C–1100°C by a rapid thermal processor(RTP). The long-term thermal stability is evaluated by aging the annealed contact at 600°C in air. The contact's properties are determined by current–voltage measurement, and the specific contact resistance is calculated based on the transmission line model(TLM). Transmission electron microscope(TEM) and energy-dispersive x-ray spectrometry(EDX) are used to characterize the interface morphology, thickness, and composition. The results reveal that a higher annealing temperature is favorable for the formation of an Ohmic contact with a lower specific contact resistance, and causes the rapid degradation of the Ohmic contact in the aging process.     

Water-based processed and alkoxide-based processed indium oxide thin-film transistors at different annealing temperatures

In this study,indium oxide(In_2O_3) thin-film transistors(TFTs) are fabricated by two kinds of low temperature solution-processed technologies(Ta ≤ 300?C),i.e.,water-based(DIW-based) process and alkoxide-based(2-ME-based)process.The thickness values,crystallization properties,chemical structures,surface roughness values,and optical properties of In_2O_3 thin-films and the electrical characteristics of In_2O_3 TFTs are studied at different annealing temperatures.Thermal annealing at higher temperature leads to an increase in the saturation mobility(μsat) and a negative shift in the threshold voltage(VTH).The DIW-based processed In_2O_3-TFT annealed at 300?C exhibits excellent device performance,and one annealed at 200?C exhibits an acceptable μsat of 0.86 cm~2/V·s comparable to that of a-Si:H TFTs,whereas the 2-ME-based TFT annealed at 300?C exhibits an abundant μsat of 1.65 cm~2/Vs and one annealed at 200?C is inactive.The results are attributed to the fact that the DIW-based process induces a higher degree of oxidation and less defect states than the 2-ME-based process at the same temperature.The DIW-based process for fabricating the In_2O_3 TFT opens the way for the development of nontoxic,low-cost,and low-temperature oxide electronics.     

Effects of active layer thickness on performance and stability of dual-active-layer amorphous InGaZnO thin-film transistors

Dual-active-layer(DAL) amorphous InGaZnO(IGZO) thin-film transistors(TFTs) are fabricated at low temperature without post-annealing. A bottom low-resistance(low-R) IGZO layer and a top high-resistance(high-R) IGZO layer constitute the DAL homojunction with smooth and high-quality interface by in situ modulation of oxygen composition. The performance of the DAL TFT is significantly improved when compared to that of a single-active-layer TFT. A detailed investigation was carried out regarding the effects of the thickness of both layers on the electrical properties and gate bias stress stabilities. It is found that the low-R layer improves the mobility, ON/OFF ratio, threshold voltage and hysteresis voltage by passivating the defects and providing a smooth interface. The high-R IGZO layer has a great impact on the hysteresis, which changes from clockwise to counterclockwise. The best TFT shows a mobility of 5.41 cm~2/V·s, a subthreshold swing of 95.0 mV/dec, an ON/OFF ratio of 6.70 × 10~7, a threshold voltage of 0.24 V, and a hysteresis voltage of 0.13 V. The value of threshold voltage shifts under positive gate bias stress decreases when increasing the thickness of both layers.     

High-photosensitivity polymer thin-film transistors based on poly（3-hexylthiophene）

Polymer thin-film transistors(PTFTs) based on poly(3-hexylthiophene) are fabricated by the spin-coating process,and their photo-sensing characteristics are investigated under steady-state visible-light illumination.The photosensitivity of the device is strongly modulated by gate voltage under various illuminations.When the device is in the subthreshold operating mode,a significant increase in its drain current is observed with a maximum photosensitivity of 1.7×10 3 at an illumination intensity of 1200 lx,and even with a relatively high photosensitivity of 611 at a low illumination intensity of 100 lx.However,when the device is in the on-state operating mode,the photosensitivity is very low:only 1.88 at an illumination intensity of 1200 lx for a gate voltage of-20 V and a drain voltage of -20 V.The results indicate that the devices could be used as photo-detectors or sensors in the range of visible light.The modulation mechanism of the photosensitivity in the PTFT is discussed in detail.     

Chemical Vapor Deposition Growth of Large-Area Monolayer MoS_2 and Fabrication of Relevant Back-Gated Transistor

A closed two-temperature-zone chemical vapor deposition(CVD) furnace was used to grow monolayer molybdenum disulfide(MoS_2) by optimizing the temperature and thus the evaporation volume of the Mo precursor. The experimental results show that the Mo precursor temperature has a large effect on the size and shape transformation of the monolayer MoS_2, and at a lower temperature of 760°C, the size of the triangular MoS_2 increases with the elevating temperature, while at a higher temperature of 760°C, the shape starts to change from a triangle to a truncated triangle. A large-area triangular monolayer MoS_2 with a side length of 145 °m is achieved at 760°C.Further, the as-grown monolayer MoS_2 is used to fabricate back-gated transistors by means of electron beam lithography to evaluate the electrical properties of MoS_2 thin films. The MoS_2 transistors with monolayer MoS_2 grown at 760°C exhibit a high on/off current ratio of 10~6, a mobility of 1.92 cm~2/Vs and a subthreshold swing of 194.6 mV/dec, demonstrating the feasible approach of CVD deposition of monolayer MoS_2 and the fabrication of transistors on it.     

Lithium niobate planar and ridge waveguides fabricated by 3 MeV oxygen ion implantation and precise diamond dicing

We report on the fabrication and optimization of lithium niobate planar and ridge waveguides at the wavelength of 633 nm.To obtain a planar waveguide, oxygen ions with an energy of 3.0 Me V and a fluence of 1.5 × 10~(15) ions=cm~2 are implanted in the polished face of Li Nb O_3 crystals. For planar waveguides, a loss of 0.5 d B/cm is obtained after annealing at 300°C for30 min. The ridge waveguide is fabricated by the diamond blade dicing method on optimized planar waveguides. The guiding properties are investigated by prism coupling and end-face coupling methods.     

Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-κ Dielectrics and SiGe Epitaxial Substrates

A novel high-κ, Al_2O_3/HfO_2/Al_2O_3 nanolaminate charge trapping memory capacitor structure based on SiGe substrates with low interface densities is successfully fabricated and investigated. The memory capacitor exhibits excellent program-erasable characteristics. A large memory window of ~4 V,a small leakage current density of ~2×10~(-6 Acm~(-2) at a gate voltage of 7 V, a high charge trapping density of 1.42 × 10~(13) cm~(-2) at a working voltage of ±10 V and good retention characteristics are observed. Furthermore, the programming(△V_(FB) = 2.8 V at 10 V for 10μs) and erasing speeds(△V_(FB)=-1.7 V at -10 V for 10μs) of the fabricated capacitor based on SiGe substrates are significantly improved as compared with counterparts reported earlier. It is concluded that the high-κ, Al_2 O_3/HfO_2/Al_2 O_3 nanolaminate charge trapping capacitor structure based on SiGe substrates is a promising candidate for future nano-scaled nonvolatile flash memory applications.