CSNS工程GPPD谱仪主探测器读出电子学的研制

中国散裂中子源(China Spallation Neutron Source,CSNS)工程通用粉末衍射谱仪(General Purpose Powder Diffractometer,GPPD)采用闪烁体探测器作为主探测器。为满足谱仪的设计需求,读出电子学系统要求在实现高达数千通道数据读出的同时,完成高精度的中子探测。基于设计目标,以及进一步提高读出系统的集成度和灵活性,读出电子学系统采用了"子板+母板"的架构。前放子板采用专用集成电路(Application Specific Integrated Circuit,ASIC)实现探测器输出信号的放大、成形、甄别等模拟调理;母板固件采用了多级流水线机制的设计方法,在保证数据并行性和可靠性的同时,进一步减小了数据处理的死时间,实现数据的采集打包、缓存等处理,最终数据通过千兆以太网传到后端数据处理系统,便于数据的分析处理。对设计实现的读出电子学系统的评估测试结果表明:最小时间分辨11 ns,单通道计数率200 K?s-1,各项指标均好于设计目标。目前所有读出电子学单元已部署到GPPD工程现场并长期稳定运行,为谱仪顺利开展实验提供了可靠保证。     

像素探测器高带宽数据获取系统设计

为适应硅像素探测器研制的需求,设计了硅像素探测器高带宽数据获取系统。该系统针对硅像素探测器高数据的特点进行了设计与优化,实现了单机高速稳定读出的数据获取目标,最高读出带宽可达到686MB/s,同时提供了控制、监测以及实验图像的实时抽样显示等功能。     

百万像素硅像素探测器数据获取系统设计

介绍了百万像素硅像素探测器数据获取系统的设计。该系统根据实验需求,尤其针对硅像素探测器1.92 GB/s高带宽的数据读出指标进行设计,实现了数据高速稳定读出的目标,同时提供运行控制、在线事例组装、无损压缩、数据存储,以及抽样显示图像等功能。文中对系统进行了稳定性以及主要性能测试,测试表明系统长期运行稳定,最高读出带宽可达2.49 GB/s。     

高计数率气体探测器读出电子学原型机研制

研制一套可用于高计数率气体探测器的读出电子学原型机系统,包括前端板、数据采集板和上位机。前端板采用一款先进的前端读出专用集成电路(ASIC)芯片实现对探测器信号的测量和模数转换;数据采集板利用现场可编程门阵列（FPGA）实现对数据的分析、处理和传输;上位机实现控制指令发送、PC端数据接收及存储等。在22~99 fC的输入范围内,原型机各通道积分非线性均好于024%;联合探测器使用55Fe放射源测试,结果好于相同条件下的商用电子学。可满足20 kHz计数率下GEM TPC探测器的读出需求。     

GEM探测器数据采集系统设计

介绍了重心读出GEM位置灵敏气体探测器中,基于USB2.0总线的数据采集电子学设备的设计及实现.采用CYPRESS公司CY7C68013A微通讯控制器、高速ADC芯片和现场可编程芯片组成的电路板,实现了数据的高速采集、高速缓存和高速串行传输.采集速率达到20 MByte/s,满足了探测器对数据采集和传输的要求.     

基于GEM探测器的数字读出芯片研制

研制了一种适用于高能物理GEM探测器读出系统的数字芯片。芯片采用PAD读出方式,对GEM探测器的输出直接采样,对采样到的信号放大并成形,判断该输入是否超过由外部DAC设定的阈值,给出判断结果,并按照一个串行协议读出。芯片采用0.35μm/3.3 V CMOS工艺设计,后仿真结果显示芯片达到预期研制目标。     

PandaX-nT暗物质探测实验读出电子学预研系统的研制

PandaX-nT升级对电子学系统提出了诸多新的挑战,如更多的通道数、高速高精度的波形数字化、灵活的触发算法和更高的数据带宽要求等。本文介绍一种为未来PandaX-nT暗物质直接探测升级实验预研的读出电子学系统。该电子学系统主要由前置放大电路模块、波形数字化模块(FDM)、数据获取模块(DAQ)和时钟分发模块等组成。FDM集成8路14 bit@1 GS/s ADC,具有较高集成度,可实现对探测器信号波形数字化,并通过光纤与DAQ通信。DAQ可汇总多块FDM数据,实现全数字化的触发算法,并通过基于TCP协议的千兆以太网与计算机通信,保证了数据传输的可靠与稳定。目前已完成了整个读出电子学系统设计,并对整个电子学系统进行了功能验证,以及与探测器进行了初步的联合测试。整个电子学系统具有较高的可扩展性,并能实现更复杂的触发算法,能满足下一代升级的需求。     

PandaX-nT暗物质探测实验读出电子学预研系统的研制

PandaX-nT升级对电子学系统提出了诸多新的挑战，如更多的通道数、高速高精度的波形数字化、灵活的触发算法和更高的数据带宽要求等。本文介绍一种为未来PandaX-nT暗物质直接探测升级实验预研的读出电子学系统。该电子学系统主要由前置放大电路模块、波形数字化模块（FDM）、数据获取模块（DAQ）和时钟分发模块等组成。FDM集成8路14 bit@ 1 GS/s ADC，具有较高集成度，可实现对探测器信号波形数字化，并通过光纤与DAQ通信。DAQ可汇总多块FDM数据，实现全数字化的触发算法，并通过基于TCP协议的千兆以太网与计算机通信，保证了数据传输的可靠与稳定。目前已完成了整个读出电子学系统设计，并对整个电子学系统进行了功能验证，以及与探测器进行了初步的联合测试。整个电子学系统具有较高的可扩展性，并能实现更复杂的触发算法，能满足下一代升级的需求。     

基于APV25多通道读出电子学系统设计

介绍了基于APV25芯片的多通道读出电子学系统的设计方法,利用ASIC芯片与可扩展读出系统相结合,实现多通道信号的处理。在该系统中,基于PXI机箱的单个读出板可实现2 048路信号的读出及处理,并具有集成度高、低功耗、可扩展等优点。电子学测试结果表明,本系统电荷输入线性动态范围为0~12 fC,APV25等效输入噪声408 e,可适应大型物理实验微结构气体探测器、硅像素探测器等探测器的读出需求。     

强子探测器快速读出系统的数据压缩和并行处理

在强子探测器快速读出系统中,由于采用了一级预相符触发的方法,达到了对数据流消零(Zero Suppression)的目的,从而大大降低了数据流量;由于采用了流水线结构(PipelineArchitecture)和高速查询表(Look-up Table)相结合的并行处理方法,二级触发器可处理数据率高达16MHz以上的数据。     

磁质谱仪离子收集器数字化读出系统的研制

研制了一个用于磁质谱仪法拉第筒阵列离子收集器的高精度数字化读出系统，实现对离子束中离子成分的分析与诊断。数字化读出系统由前端处理电路和数据获取模块组成，前端处理电路采用门控积分器将418通道微弱电荷信号转换为电压信号，数据获取模块将电压信号数字化后，通过以太网接口将数据上传到远程上位机。该读出系统实现了电荷范围为0.1~120 pC的数字化读出，非线性误差小于1.95%（全量程）。现场应用测试结果表明，该数字化读出系统完全满足实验需求。该系统还可广泛用于核物理实验和加速器系统中微弱电流或电荷信号的测量。     

LRAD测量管道内α污染活度的BP网络模拟

针对风速、流量、探源距、测试管管长和管径等因素对核设施退役中管道内α污染测量造成的非线性影响,采用控制变量法开展长距离α测量(Long range alpha detector,LRAD)模拟装置下的多参数影响实验,初步分析了各种因素对系统测量值的影响特征,建立了以影响因素和测量值为输入、放射源活度为输出的BP神经网络模型,分别对948和100组数据进行了模型建立和实例检验,结果说明,预测平均相对误差为3.4218×10–4,实例平均相对误差为2.217×10–2。应用BP网络模型模拟LRAD装置下的α活度是可行且有效的。     

LHAASO-WFCTA多通道数据高速传输方案设计

为解决广角大气荧光/切伦科夫光探测器阵列电子学读出系统板间多通道数据传输问题,设计了一种基于低压差分信号接口的同步串行传输方案,给出了误码率及稳定性测试。测试结果表明,在125MHz时钟频率下,传输误码率小于10~(-12),且具有较高的稳定性,能够较好的满足系统数据传输需求。     

Development of readout electronics for bunch arrival-time monitor system at SXFEL

A bunch arrival-time monitor(BAM) system,based on electro-optical intensity modulation scheme, is under study at Shanghai Soft X-ray Free Electron Laser.The aim of the study is to achieve high-precision time measurement for minimizing bunch fluctuations. A readout electronics is developed to fulfill the requirements of the BAM system. The readout electronics is mainly composed of a signal conditioning circuit, field-programmable gate array(FPGA), mezzanine card(FMC150), and powerful FPGA carrier board. The signal conditioning circuit converts the laser pulses into electrical pulse signals using a photodiode. Thereafter, it performs splitting and low-noise amplification to achieve the best voltage sampling performance of the dual-channel analog-to-digital converter(ADC) in FMC150. The FMC150 ADC daughter card includes a 14-bit 250 Msps dual-channel high-speed ADC,a clock configuration, and a management module. The powerful FPGA carrier board is a commercial high-performance Xilinx Kintex-7 FPGA evaluation board. To achieve clock and data alignment for ADC data capture at a high sampling rate, we used ISERDES, IDELAY, and dedicated carry-in resources in the Kintex-7 FPGA. This paper presents a detailed development of the readout electronics in the BAM system and its performance.     

Multichannel acquisition system for high-resolution position-sensing silicon drift detectors

We present the design guidelines and the experimental characterization of a multichannel acquisition system that measures the amplitude and the time-of-arrival of the signal pulses delivered by position-sensing silicon drift detectors (SDDs). The readout system has been equally developed for multichannel SDDs and for controlled drift detectors (CDDs) intended for spectroscopic imaging of X-rays or charged particles. The analog section includes a very large scale integration (VLSI) front-end preamplifier and bias current generator for the on-chip JFET follower while the digital back-end is realized with 12 bit 100 MS/s 8-channel analog-to-digital converter (ADC) versa modular eurocard (VME) boards. Amplitude and time are measured by digitally processing each unipolar shaped pulse also in presence of a superposed background waveform. The VME modularity allows the expansion of the readout system up to 128 channels per VME crate. The overall linearity error is better than 0.05%, and the mean noise over all channels, expressed in terms of equivalent noise charge, is about 4 electrons r.m.s. The measured time resolution is 0.6 ns r.m.s. at a signal charge of 5000 electrons, corresponding to a position resolution of 2-3 /spl mu/m r.m.s. along the drift direction. The developed readout system has been used for X-ray imaging tests with CDDs at Sincrotrone Trieste.     

Front End Processing for a 100 MHz Flash-ADC-System

An intelligent interface for readout of a high speed (100 MHz), multichannel Flash-ADC System [1] is described. 3072 FADC channels are controlled and read by a system of 34 microprocessors M68000 placed at two different hierarchical levels. In addition to the readout itself, the processors perform a detailed pulse shape analysis neccessary for a compact and manageable data format. The purpose of the system is to exploit the good double track separation and time resolution provided by Flash-ADCs in conjunction with large drift chamber detectors such as JADE at PETRA [2] and OPAL at LEP [3]. Details of the system presently being installed at JADE are reviewed.     

Design and offline processing of an ultrafast digitizer based on internal cascaded DRS4

In this paper, we present an ultrafast digitizer utilizing the DRS4 switched capacitor array applicationspecific integrated circuit to achieve an ultrafast sampling speed of at most 5 GS/s. We cascaded all eight channels(sub-channels) of a single DRS4 chip for increased storage depth. The digitizer contains four DRS4 chips, a quadchannel analog-to-digital converter,a controlling fieldprogrammable gate array, a PXI interface, and an SFP+connector. Consequently, each DRS4 channel has a depth of 8192 points and a vertical resolution of 14 bits. The readout sequences should be broken into several segments and then reordered to obtain the correct sequential data sets, and this offline procedure varies in different readout modes. This paper describes the design and implementation of the hardware; in particular, the respective processing procedures are described in detail. Furthermore, the offset error is calibrated and corrected to improve the precision of the captured waveform in both single-channel and highresolution modes.     

GERO: a general SCA-based readout ASIC for micro-pattern gas detectors with configurable storage depth and on-chip digitizer

The paper presents GEneral Read Out(GERO), a general readout ASIC based on a switched capacitor array for micro-pattern gas detectors. It aims at providing general readout electronics for low-to-medium event-rate gas detectors with high sampling frequency, configurable storage depth, and data digitalization. The first prototype GERO chip integrates 16 channels and was fabricated using a 0.18-lm CMOS process. Each channel consists of a sampling array working in a ping-pong mode, a storage array with a 1024-cell depth, and 32 Wilkinson analog-todigital converters. The detailed design and test results are presented in the paper.