In-situ detection of C-reactive protein using silicon nanowire field effect transistor

Label-free, sensitive, and real-time c-reactive protein (CRP) sensor was fabricated using p-type silicon nanowire (SiNW) based structures configured as field effect transistors (FET) using the conventional 'top-down' semiconductor processes. The width of SiNWs were distributed 80 nm to 400 nm. Among them to improve signal-to-noise ratio and sensitivity of SiNW FET, 221 nm-SiNW was chosen for biosensing of CRP. Antibody of c-reactive protein (anti-CRP) was immobilized on the SiNW surface through polydimethylsiloxane (PDMS) microfluidic channel for detection of CRP. Specific binding of CRP with anti-CRP on the SiNW surface caused a conductance change of SiNW FET and various injections from 10 and 1 microg/ml to 100 ng/ml solutions of CRP resulted in the conductance changes from 39 and 25 to 16%, respectively. Label-free, in-situ and very sensitive electrical detection of CRP was demonstrated with the prepared SiNW FET.     

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

Abstract

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.     

Novel nonvolatile memory with multibit storage based on a ZnO nanowire transistor

We demonstrate a room temperature processed ferroelectric (FE) nonvolatile memory based on a ZnO nanowire (NW) FET where the NW channel is coated with FE nanoparticles. A single device exhibits excellent memory characteristics with the large modulation in channel conductance between ON and OFF states exceeding 10(4), a long retention time of over 4 × 10(4) s, and multibit memory storage ability. Our findings provide a viable way to create new functional high-density nonvolatile memory devices compatible with simple processing techniques at low temperature for flexible devices made on plastic substrates.     

Hybrid Si nanowire/amorphous silicon FETs for large-area image sensor arrays

Silicon nanowire (SiNW) field-effect transistors (FETs) were fabricated from nanowire mats mechanically transferred from a donor growth wafer. Top- and bottom-gate FET structures were fabricated using a doped a-Si:H thin film as the source/drain (s/d) contact. With a graded doping profile for the a-Si:H s/d contacts, the off-current for the hybrid nanowire/thin-film devices was found to decrease by 3 orders of magnitude. Devices with the graded contacts had on/off ratios of ～10(5), field-effect mobility of ～50 cm(2)/(V s), and subthreshold swing of 2.5 V/decade. A 2 in. diagonal 160 × 180 pixel image sensor array was fabricated by integrating the SiNW backplane with an a-Si:H p-i-n photodiode.     

Single and tandem axial p-i-n nanowire photovoltaic devices

Nanowires represent a promising class of materials for exploring new concepts in solar energy conversion. Here we report the first experimental realization of axial modulation-doped p-i-n and tandem p-i-n(+) -p(+)-i-n silicon nanowire (SiNW) photovoltaic elements. Scanning electron microscopy images of selectively etched nanowires demonstrate excellent synthetic control over doping and lengths of distinct regions in the diode structures. Current-voltage (I-V) characteristics reveal clear and reproducible diode characteristics for the p-i-n and p-n SiNW devices. Under simulated one-sun solar conditions (AM 1.5G), optimized p-i-n SiNW devices exhibited an open circuit voltage (Voc) of 0.29 V, a maximum short-circuit current density of 3.5 mA/cm(2), and a maximum efficiency of 0.5%. The response of the short-circuit current versus Voc under varying illumination intensities shows that the diode quality factor is improved from n=1.78 to n=1.28 by insertion of the i-type SiNW segment. The temperature dependence of Voc scales as -2.97 mV/K and extrapolates to the crystalline Si band gap at 0 K, which is in excellent agreement with bulk properties. Finally, a novel single SiNW tandem solar cell consisting of synthetic integration of two photovoltaic elements with an overall p-i-n(+) -p(+)-i-n structure was prepared and shown to exhibit a Voc that is on average 57% larger than that of the single p-i-n device. Fundamental studies of such well-defined nanowire photovoltaics will enable their intrinsic performance limits to be defined.     

Fabrication of flexible and vertical silicon nanowire electronics

Vertical silicon nanowire (SiNW) array devices directly connected on both sides to metallic contacts were fabricated on various non-Si-based substrates (e.g., glass, plastics, and metal foils) in order to fully exploit the nanomaterial properties for final applications. The devices were realized with uniform length Ag-assisted electroless etched SiNW arrays that were detached from their fabrication substrate, typically Si wafers, reattached to arbitrary substrates, and formed with metallic contacts on both sides of the NW array. Electrical characterization of the SiNW array devices exhibits good current-voltage characteristics consistent with the SiNW morphology.     

High performance ring oscillators from 10-nm wide silicon nanowire field-effect transistors

We explore 10-nm wide Si nanowire (SiNW) field-effect transistors (FETs) for logic applications, via the fabrication and testing of SiNW-based ring oscillators. We report on SiNW surface treatments and dielectric annealing, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratio (∼10⁸), low drain-induced barrier lowering (∼30 mV) and low subthreshold swing (∼80 mV/decade). The performance of inverter and ring-oscillator circuits fabricated from these nanowire FETs are also explored. The inverter demonstrates the highest voltage gain (∼148) reported for a SiNW-based NOT gate, and the ring oscillator exhibits near rail-to-rail oscillation centered at 13.4 MHz. The static and dynamic characteristics of these NW devices indicate that these SiNW-based FET circuits are excellent candidates for various high-performance nanoelectronic applications.      

A dielectric-modulated field-effect transistor for biosensing

Interest in biosensors based on field-effect transistors (FETs), where an electrically operated gate controls the flow of charge through a semiconducting channel, is driven by the prospect of integrating biodetection capabilities into existing semiconductor technology. In a number of proposed FET biosensors, surface interactions with biomolecules in solution affect the operation of the gate or the channel. However, these devices often have limited sensitivity. We show here that a FET biosensor with a vertical gap is sensitive to the specific binding of streptavidin to biotin. The binding of the streptavidin changes the dielectric constant (and capacitance) of the gate, resulting in a large shift in the threshold voltage for operating the FET. The vertical gap is fabricated using simple thin-film deposition and wet-etching techniques. This may be an advantage over planar nanogap FETs, which require lithographic processing. We believe that the dielectric-modulated FET (DMFET) provides a useful approach towards biomolecular detection that could be extended to a number of other systems.     

Enhanced channel modulation in dual-gated silicon nanowire transistors

Dual-gated silicon nanowire (SiNW) field-effect transistors (FETs) have been fabricated by using electron-beam lithography. SiNW devices (W approximately 60 nm) exhibit an on/off current ratio greater than 10(6), which is more than 3 orders of magnitude higher than that of control devices prepared simultaneously having a large channel width (approximately 5 microm). In addition, by changing the local energy-band profile of the SiNW channel, the top gate is found to suppress ambipolar conduction effectively, which is one of the factors limiting the use of nanotube or nanowire FETs for complimentary logic applications. Two-dimensional numerical simulations show that the gate-induced electrostatic control is improved as the channel width of the FETs decreases. Therefore, enhanced channel modulations can be achieved in these dual-gated SiNW devices.     

Low-concentration NO/sub 2/ detection with an adsorption porous silicon FET

Adsorption porous silicon FET (APSFET) is a porous silicon (PS)-based device constituted of a FET structure with a porous adsorbing layer between drain and source. Adsorbed gas molecules in the porous layer induce an inverted channel in the crystalline silicon under the PS itself. The mobile charge per unit area in the channel depends on the molecular gas concentrations in the sensing layer so that adsorbed gas molecules play a role similar to the charge on the gate of a FET. In this work, NO/sub 2/ detection by using the APSFET is demonstrated for the first time. NO/sub 2/ concentration as low as 100 ppb was detected. Devices with both as-grown and oxidized PS layers were fabricated and compared in order to investigate the effect of a low-temperature thermal oxidation on the electrical performances of the sensor. Nonoxidized sensors show a high sensitivity only for fresh devices, which reduces with the aging of the sample. Oxidation of the PS layer improves the electrical performance of sensors, in terms of stability, recovery time, and interference with the relative humidity level, keeping the high sensitivity to nitrogen dioxide.     

Reducing the contact resistance of SiNW devices by employing a heavily doped carrier injection layer

Silicon nanowires (SiNWs) are promising building blocks for future electronic devices. In SiNW-based devices, reducing the contact resistance of SiNW-metal as much as possible is critically important. Here we report a simple fabrication approach for SiNW field effect transistors (FETs) with low contact resistances by employing a heavily doped carrier injection layer wrapped around SiNWs at the contact region. Both n- and p-type SiNW-FET devices with carrier injection layers were investigated, the contact resistances were one order smaller than those without carrier injection layers and only contribute less than 14.8% for n-type devices and 11.4% for p-type devices, respectively, to the total resistance. Such low contact resistance guarantees the device characteristics mainly from the channel region of SiNW-based devices.     

Transformable functional nanoscale building blocks with wafer-scale silicon nanowires

Through the fusion of electrostatics and mechanical dynamics, we demonstrate a transformable silicon nanowire (SiNW) field effect transistor (FET) through a wafer-scale top-down approach. By felicitously taking advantage of the proposed electrostatic SiNW-FET with mechanically movable SiNWs, all essential logic gates, including address decoders, can be monolithically integrated into a single device. The unification of various functional devices, such as pn-diodes, FETs, logic gates, and address decoders, can therefore eliminate the complex fabrication issues associated with nanoscale integration. These results represent a step toward the creation of multifunctional and flexible nanoelectronics.     

Fabrication and characterization of nano-channel field effect transistors patterned by AFM anodic oxidation

We report a top-down approach based on atomic force microscope (AFM) local anodic oxidation (LAO) for the fabrications of the nanowire and nano-ribbon field effect transistors (FETs). In order to investigate the transport characteristics of nano-channel, we fabricated simple FET structures with channel width W approximately 300 nm (nanowire) and 10 microm (nano-ribbon) on 20 nm-thick silicon-on-insulator (SOL) wafers. In order to investigate the transport behavior in the device with different channel geometries, we have performed detailed two-dimensional simulations of nanowire and reference nano-ribbon FETs with a fixed channel length L and thickness t but varying channel width W from 300 nm to 10 microm. By evaluating the charge distributions, we have shown that the increase of 'on state' conduction current in SiNW channel is a dominant factor, which consequently result in the improved on/off current ratio of the nanowire FET.     

Effect of self-assembled monolayers on charge injection and transport in poly(3-hexylthiophene)-based field-effect transistors at different channel length scales

Charge injection and transport in bottom-contact regioregular-poly(3-hexylthiophene) (rr-P3HT) based field-effect transistors (FETs), wherein the Au source and drain contacts are modified by self-assembled monolayers (SAMs), is reported at different channel length scales. Ultraviolet photoelectron spectroscopy is used to measure the change in metal work function upon treatment with four SAMs consisting of thiol-adsorbates of different chemical composition. Treatment of FETs with electron-poor (electron-rich) SAMs resulted in an increase (decrease) in contact metal work function because of the electron-withdrawing (-donating) tendency of the polar molecules. The change in metal work function affects charge injection and is reflected in the form of the modulation of the contact resistance, R(C). For example, R(C) decreased to 0.18 MΩ in the case of the (electron-poor) 3,5-bis-trifluoromethylbenzenethiol treated contacts from the value of 0.61 MΩ measured in the case of clean Au-contacts, whereas it increased to 0.97 MΩ in the case of the (electron-rich) 3-thiomethylthiophene treated contacts. Field-effect mobility values are observed to be affected in short-channel devices (<20 μm) but not in long-channel devices. This channel-length-dependent behavior of mobility is attributed to grain-boundary limited charge transport at longer channel lengths in these devices.     

Observation of diameter dependent carrier distribution in nanowire-based transistors

The successful implementation of nanowire (NW) based field-effect transistors (FET) critically depends on quantitative information about the carrier distribution inside such devices. Therefore, we have developed a method based on high-vacuum scanning spreading resistance microscopy (HV-SSRM) which allows two-dimensional (2D) quantitative carrier profiling of fully integrated silicon NW-based tunnel-FETs (TFETs) with 2 nm spatial resolution. The key elements of our characterization procedure are optimized NW cleaving and polishing steps, the use of in-house fabricated ultra-sharp diamond tips, measurements in high vacuum and a dedicated quantification procedure accounting for the Schottky-like tip-sample contact affected by surface states. In the case of the implanted TFET source regions we find a strong NW diameter dependence of conformality, junction abruptness and gate overlap, quantitatively in agreement with process simulations. In contrast, the arsenic doped drain regions reveal an unexpected NW diameter dependent dopant deactivation. The observed lower drain doping for smaller diameters is reflected in the device characteristics by lower TFET off-currents, as measured experimentally and confirmed by device simulations.     

Controlled synthesis of millimeter-long silicon nanowires with uniform electronic properties

We report the nanocluster-catalyzed growth of ultralong and highly uniform single-crystalline silicon nanowires (SiNWs) with millimeter-scale lengths and aspect ratios up to approximately 100 000. The average SiNW growth rate using disilane (Si 2H 6) at 400 degrees C was 31 mum/min, while the growth rate determined for silane (SiH 4) reactant under similar growth conditions was 130 times lower. Transmission electron microscopy studies of millimeter-long SiNWs with diameters of 20-80 nm show that the nanowires grow preferentially along the 110 direction independent of diameter. In addition, ultralong SiNWs were used as building blocks to fabricate one-dimensional arrays of field-effect transistors (FETs) consisting of approximately 100 independent devices per nanowire. Significantly, electrical transport measurements demonstrated that the millimeter-long SiNWs had uniform electrical properties along the entire length of wires, and each device can behave as a reliable FET with an on-state current, threshold voltage, and transconductance values (average +/-1 standard deviation) of 1.8 +/- 0.3 muA, 6.0 +/- 1.1 V, 210 +/- 60 nS, respectively. Electronically uniform millimeter-long SiNWs were also functionalized with monoclonal antibody receptors and used to demonstrate multiplexed detection of cancer marker proteins with a single nanowire. The synthesis of structurally and electronically uniform ultralong SiNWs may open up new opportunities for integrated nanoelectronics and could serve as unique building blocks linking integrated structures from the nanometer through millimeter length scales.     

Experimental Comparison Between Sub-0.1-μm Ultrathin SOI Single- and Double-Gate MOSFETs: Performance and Mobility

This paper presents an experimental comparison between single-gate (SG) and double-gate (DG) transistors performance. Using a novel process flow, we managed to cointegrate these two devices on the same wafer with a TiN metal gate. Short-channel effect control, static performance, and mobility are quantified for each architecture. An in-depth mobility study is performed for a wide range of temperatures (10 K-300 K) and gate lengths (10-20 nm) while channel thickness is fixed at 6 nm. This study experimentally highlights the advantages of DG devices over SG transistors. Good mobility values are obtained for both architectures and we show the advantages of ultrathin body devices over bulk transistors. Finally, we demonstrate that Coulomb scattering is the primary cause of the mobility degradation in short-channel devices     

Electrostatic Limit of Detection of Nanowire‐Based Sensors

Scanning gate microscopy is used to determine the electrostatic limit of detection (LOD) of a nanowire (NW) based chemical sensor with a precision of sub‐elementary charge. The presented method is validated with an electrostatically formed NW whose active area and shape are tunable by biasing a multiple gate field‐effect transistor (FET). By using the tip of an atomic force microscope (AFM) as a local top gate, the field effect of adsorbed molecules is emulated. The tip induced charge is quantified with an analytical electrostatic model and it is shown that the NW sensor is sensitive to about an elementary charge and that the measurements with the AFM tip are in agreement with sensing of ethanol vapor. This method is applicable to any FET‐based chemical and biological sensor, provides a means to predict the absolute sensor performance limit, and suggests a standardized way to compare LODs and sensitivities of various sensors.     

Measurement of carrier mobility in silicon nanowires

We report the first direct capacitance measurements of silicon nanowires (SiNWs) and the consequent determination of field carrier mobilities in undoped-channel SiNW field-effect transistors (FETs) at room temperature. We employ a two-FET method for accurate extraction of the intrinsic channel resistance and intrinsic channel capacitance of the SiNWs. The devices used in this study were fabricated using a top-down method to create SiNW FETs with up to 1000 wires in parallel for increasing the raw capacitance while maintaining excellent control on device dimensions and series resistance. We found that, compared with the universal mobility curves for bulk silicon, the electron and hole mobilities in nanowires are comparable to those of the surface orientation that offers a lower mobility.     

A facile method for fabrication of large area graphene nanostructures

In this study, we introduce a novel method to produce large area interconnected graphene nanostructures. A single layer CVD (Chemical Vapor Deposition) grown graphene was nanostructured by employing dewetted Ni thin film as an etching mask for the underlying graphene. As a result, a network of graphene nanostructures with irregular shapes and widths down to 10 nm is obtained. The FET (field effect transistor) devices fabricated employing the nanostructured graphene as channel material exhibit increased on/off current ratio compared to pristine graphene indicating a slight band gap opening due to the quantum confinement effect in such narrow graphene nanostructures. This technique can be useful for the large scale fabrication of graphene based electronic devices such as FETs and sensors.